ATTINY44-20MUR Atmel, ATTINY44-20MUR Datasheet - Page 78
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ATTINY44-20MUR
Manufacturer Part Number
ATTINY44-20MUR
Description
MCU AVR 4KB FLASH 20MHZ 20QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY24-20MU.pdf
(238 pages)
Specifications of ATTINY44-20MUR
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY44-20MUR
Manufacturer:
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11.8
78
Timer/Counter Timing Diagrams
ATtiny24/44/84
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The
Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM
value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the
OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM. An inverted
PWM output can be generated by setting the COM0x1:0 to three: Setting the COM0A0 bits to
one allows the OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is
not available for the OC0B pin (See
visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is
generated by clearing (or setting) the OC0x Register at the Compare Match between OCR0x
and TCNT0 when the counter increments, and setting (or clearing) the OC0x Register at Com-
pare Match between OCR0x and TCNT0 when the counter decrements. The PWM frequency for
the output when using phase correct PWM can be calculated by the following equation:
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR0A Register represent special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCR0A is set equal to BOTTOM, the
output will be continuously low and if set equal to MAX the output will be continuously high for
non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.
At the very start of period 2 in
even though there is no Compare Match. The point of this transition is to guaratee symmetry
around BOTTOM. There are two cases that give a transition without Compare Match.
The Timer/Counter is a synchronous design and the timer clock (clk
clock enable signal in the following figures. The figures include information on when Interrupt
Flags are set.
The figure shows the count sequence close to the MAX value in all modes other than phase cor-
rect PWM mode.
• OCR0A changes its value from MAX, like in
• The timer starts counting from a value higher than the one in OCR0A, and for that reason
is MAX the OCn pin value is the same as the result of a down-counting Compare Match. To
ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result of
an up-counting Compare Match.
misses the Compare Match and hence the OCn change that would have happened on the
way up.
Figure 11-8 on page 79
Figure 11-7 on page 77
f
Table 11-4 on page
OCnxPCPWM
contains timing data for basic Timer/Counter operation.
Figure 11-7 on page
=
----------------- -
N 510
f
clk_I/O
⋅
81). The actual OC0x value will only be
OCn has a transition from high to low
77. When the OCR0A value
T0
) is therefore shown as a
8006K–AVR–10/10
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