ATMEGA48A-MMHR Atmel, ATMEGA48A-MMHR Datasheet - Page 295
ATMEGA48A-MMHR
Manufacturer Part Number
ATMEGA48A-MMHR
Description
IC MCU AVR 4K FLASH 28QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA48A-MMHR.pdf
(566 pages)
Specifications of ATMEGA48A-MMHR
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Speed
20MHz
Number Of I /o
23
Eeprom Size
256 x 8
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
512 x 8
Program Memory Size
4KB (4K x 8)
Data Converters
A/D 8x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Connectivity
I²C, SPI, UART/USART
Core Size
8-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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ATmega48A/48PA/88A/88PA/168A/168PA/328/328
address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The
PGWRT bit will auto-clear upon completion of a Page Write, or if no SPM instruction is executed
within four clock cycles. The CPU is halted during the entire Page Write operation if the NRWW
section is addressed.
• Bit 1 – PGERS: Page Erase
If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction within four
clock cycles executes Page Erase. The page address is taken from the high part of the Z-
pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a
Page Erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted dur-
ing the entire Page Write operation if the NRWW section is addressed.
• Bit 0 – SELFPRGEN: Self Programming Enable
This bit enables the SPM instruction for the next four clock cycles. If written to one together with
either RWWSRE, BLBSET, PGWRT or PGERS, the following SPM instruction will have a spe-
cial meaning, see description above. If only SELFPRGEN is written, the following SPM
instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer.
The LSB of the Z-pointer is ignored. The SELFPRGEN bit will auto-clear upon completion of an
SPM instruction, or if no SPM instruction is executed within four clock cycles. During Page Erase
and Page Write, the SELFPRGEN bit remains high until the operation is completed.
Writing any other combination than “10001”, “01001”, “00101”, “00011” or “00001” in the lower
five bits will have no effect.
295
8271C–AVR–08/10
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