AT90PWM1-16SU Atmel, AT90PWM1-16SU Datasheet - Page 161
![MCU AVR 8K FLASH 16MHZ 24-SOIC](/photos/6/70/67046/453-24-soic_sml.jpg)
AT90PWM1-16SU
Manufacturer Part Number
AT90PWM1-16SU
Description
MCU AVR 8K FLASH 16MHZ 24-SOIC
Manufacturer
Atmel
Series
AVR® 90PWM Lightingr
Datasheet
1.AT90PWM1-16SU.pdf
(297 pages)
Specifications of AT90PWM1-16SU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
19
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
24-SOIC (7.5mm Width)
Processor Series
AT90PWMx
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SPI
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
19
Number Of Timers
2
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRFBKIT, ATAVRISP2
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 11 Channel
For Use With
ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT90PWM1-16SU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- Current page: 161 of 297
- Download datasheet (4Mb)
16.25.13 PSC n Input A Control Register – PFRCnA
16.25.14 PSC n Input B Control Register – PFRCnB
4378C–AVR–09/08
• Bit 1 – PCCYC2 : PSC 2 Complete Cycle
When this bit is set, the PSC 2 completes the entire waveform cycle before halt operation
requested by clearing PRUN2. This bit is not relevant in slave mode (PARUN2 = 1).
• Bit 0 – PRUN2 : PSC 2 Run
Writing this bit to one starts the PSC 2.
When set, this bit prevails over PARUN2 bit.
The Input Control Registers are used to configure the 2 PSC’s Retrigger/Fault block A & B. The
2 blocks are identical, so they are configured on the same way.
• Bit 7 – PCAEnx : PSC n Capture Enable Input Part x
Writing this bit to one enables the capture function when external event occurs on input selected
as input for Part x (see PISELnx bit in the same register).
• Bit 6 – PISELnx : PSC n Input Select for Part x
Clear this bit to select PSCINn as input of Fault/Retrigger block x.
Set this bit to select Comparator n Output as input of Fault/Retrigger block x.
• Bit 5 –PELEVnx : PSC n Edge Level Selector of Input Part x
When this bit is clear, the falling edge or low level of selected input generates the significative
event for retrigger or fault function .
When this bit is set, the rising edge or high level of selected input generates the significative
event for retrigger or fault function.
• Bit 4 – PFLTEnx : PSC n Filter Enable on Input Part x
Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is
activated, the input from the retrigger pin is filtered. The filter function requires four successive
equal valued samples of the retrigger pin for changing its output. The Input Capture is therefore
delayed by four oscillator cycles when the noise canceler is enabled.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
PCAEnA
PCAEnB
R/W
R/W
7
0
7
0
PISELnA
PISELnB
R/W
R/W
6
0
6
0
PELEVnA
PELEVnB
R/W
R/W
5
0
5
0
PFLTEnA
PFLTEnB
R/W
R/W
4
0
4
0
PRFMnA3 PRFMnA2 PRFMnA1 PRFMnA0
PRFMnB3 PRFMnB2 PRFMnB1 PRFMnB0
R/W
R/W
3
0
3
0
R/W
R/W
2
0
2
0
R/W
R/W
1
0
1
0
AT90PWM1
R/W
R/W
0
0
0
0
PFRCnA
PFRCnB
161
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