ATMEGA16U2-MU Atmel, ATMEGA16U2-MU Datasheet - Page 109

• Manufacturer Part Number: ATMEGA16U2-MU
• Description: MCU AVR 16K FLASH USB 32-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA16U2-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Core: AVR8
• Processor Series: ATMEGA16x
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 16 MHz
• Data Ram Size: 1.25 KB
• Data Rom Size: 512 B
• Number Of Programmable I/os: 22
• Number Of Timers: 2
• Mounting Style: SMD/SMT
• Height: 0.95 mm
• Interface Type: SPI, UART
• Length: 5 mm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 5 mm
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

16.2.1
7799D–AVR–11/10
Registers
Figure 16-1. 16-bit Timer/Counter Block Diagram
Note:
The Timer/Counter (TCNTn), Output Compare Registers (OCRnA/B/C), and Input Capture Reg-
ister (ICRn) are all 16-bit registers. Special procedures must be followed when accessing the 16-
bit registers. These procedures are described in the section
page
CPU access restrictions. Interrupt requests (shorten as Int.Req.) signals are all visible in the
Timer Interrupt Flag Register (TIFRn). All interrupts are individually masked with the Timer Inter-
rupt Mask Register (TIMSKn). TIFRn and TIMSKn are not shown in the figure since these
registers are shared by other timer units.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on
the Tn pin. The Clock Select logic block controls which clock source and edge the Timer/Counter
uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source
is selected. The output from the clock select logic is referred to as the timer clock (clk
The double buffered Output Compare Registers (OCRnA/B/C) are compared with the
Timer/Counter value at all time. The result of the compare can be used by the Waveform Gener-
ator to generate a PWM or variable frequency output on the Output Compare pin (OCnA/B/C).
110. The Timer/Counter Control Registers (TCCRnA/B/C) are 8-bit registers and have no
1. Refer to
Timer/Counter1 pin placement and description.
Figure 1-1 on page
Timer/Counter
OCRnB
TCCRnA
OCRnA
OCRnC
TCNTn
ICRn
=
=
=
Direction
2,
Count
Clear
Table 12-3 on page
Control Logic
TOP
=
TCCRnB
Values
BOTTOM
Fixed
TOP
ATmega8U2/16U2/32U2
(1)
ICFn (Int.Req.)
TCLK
Detector
Edge
=
0
74, and
“Accessing 16-bit Registers” on
OCFnA
(Int.Req.)
OCFnB
(Int.Req.)
OCFnC
(Int.Req.)
Table 12-6 on page 77
TOVn
(Int.Req.)
Clock Select
Generation
Generation
Generation
( From Prescaler )
Waveform
Waveform
Waveform
TCCRnC
Canceler
Detector
Noise
Edge
Comparator Ouput )
( From Analog
OCnA
OCnB
OCnC
ICPn
Tn
T
for
n
).
109