AT90PWM316-16SUR Atmel, AT90PWM316-16SUR Datasheet - Page 175
![MCU AVR 16K FLASH 16MHZ 32-SOIC](/photos/7/29/72992/313-32-soic_sml.jpg)
AT90PWM316-16SUR
Manufacturer Part Number
AT90PWM316-16SUR
Description
MCU AVR 16K FLASH 16MHZ 32-SOIC
Manufacturer
Atmel
Series
AVR® 90PWM Lightingr
Datasheet
1.AT90PWM216-16SU.pdf
(359 pages)
Specifications of AT90PWM316-16SUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
27
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 11x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
32-SOIC (7.5mm Width)
For Use With
ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOICATAVRMC200 - KIT EVAL FOR AT90PWM3 ASYNCATAVRFBKIT - KIT DEMO BALLAST FOR AT90PWM2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
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17. Serial Peripheral Interface – SPI
17.1
7710E–AVR–08/10
Features
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the
AT90PWM216/316 and peripheral devices or between several AVR devices.
The AT90PWM216/316 SPI includes the following features:
•
•
•
•
•
•
•
•
Figure 17-1. SPI Block Diagram
Note:
The interconnection between Master and Slave CPUs with SPI is shown in
tem consists of two shift Registers, and a Master clock generator. The SPI Master initiates the
communication cycle when pulling low the Slave Select SS pin of the desired Slave. Master and
Full-duplex, Three-wire Synchronous Data Transfer
Master or Slave Operation
LSB First or MSB First Data Transfer
Seven Programmable Bit Rates
End of Transmission Interrupt Flag
Write Collision Flag Protection
Wake-up from Idle Mode
Double Speed (CK/2) Master SPI Mode
1. Refer to
/2/4/8/16/32/64/128
DIVIDER
clk
Figure 3-1 on page
IO
(1)
3, and
Table 11-3 on page 67
AT90PWM216/316
for SPI pin placement.
Figure
17-2. The sys-
SPIPS
SS_A
MISO
MISO
_A
MOSI
MOSI
_A
SCK
_A
175
SCK
SS
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