ATMEGA88-20MUR Atmel, ATMEGA88-20MUR Datasheet - Page 184

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ATMEGA88-20MUR

Manufacturer Part Number
ATMEGA88-20MUR
Description
MCU AVR 8K FLASH 20MHZ 32QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA88-20MUR

Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
20MHz
Interface Type
SPI/TWI/USART
Total Internal Ram Size
1KB
# I/os (max)
23
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
32
Package Type
MLF EP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
19.7.6
19.7.7
19.8
19.8.1
184
Asynchronous Data Reception
ATmega48/88/168
Disabling the Receiver
Flushing the Receive Buffer
Asynchronous Clock Recovery
The UPEn bit is set if the next character that can be read from the receive buffer had a Parity
Error when received and the Parity Checking was enabled at that point (UPMn1 = 1). This bit is
valid until the receive buffer (UDRn) is read.
In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing
receptions will therefore be lost. When disabled (that is, the RXENn is set to zero) the Receiver
will no longer override the normal function of the RxDn port pin. The Receiver buffer FIFO will be
flushed when the Receiver is disabled. Remaining data in the buffer will be lost
The receiver buffer FIFO will be flushed when the Receiver is disabled, that is, the buffer will be
emptied of its contents. Unread data will be lost. If the buffer has to be flushed during normal
operation, due to for instance an error condition, read the UDRn I/O location until the RXCn Flag
is cleared. The following code example shows how to flush the receive buffer.
Note:
The USART includes a clock recovery and a data recovery unit for handling asynchronous data
reception. The clock recovery logic is used for synchronizing the internally generated baud rate
clock to the incoming asynchronous serial frames at the RxDn pin. The data recovery logic sam-
ples and low pass filters each incoming bit, thereby improving the noise immunity of the
Receiver. The asynchronous reception operational range depends on the accuracy of the inter-
nal baud rate clock, the rate of the incoming frames, and the frame size in number of bits.
The clock recovery logic synchronizes internal clock to the incoming serial frames.
illustrates the sampling process of the start bit of an incoming frame. The sample rate is 16 times
the baud rate for Normal mode, and eight times the baud rate for Double Speed mode. The hor-
izontal arrows illustrate the synchronization variation due to the sampling process. Note the
larger time variation when using the Double Speed mode (U2Xn = 1) of operation. Samples
denoted zero are samples done when the RxDn line is idle (that is, no communication activity).
Assembly Code Example
C Code Example
USART_Flush:
void USART_Flush( void )
{
}
sbis UCSRnA, RXCn
ret
in
rjmp USART_Flush
unsigned char dummy;
while ( UCSRnA & (1<<RXCn) ) dummy = UDRn;
1.
See ”About Code Examples” on page 7.
r16, UDRn
(1)
(1)
2545S–AVR–07/10
Figure 19-5

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