PIC16F1938-I/SO Microchip Technology, PIC16F1938-I/SO Datasheet - Page 370
PIC16F1938-I/SO
Manufacturer Part Number
PIC16F1938-I/SO
Description
IC MCU 8BIT FLASH 28SOIC
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheets
1.PIC16F722-ISS.pdf
(8 pages)
2.PIC16LF1933-ISS.pdf
(508 pages)
3.PIC16LF1933-ISS.pdf
(46 pages)
4.PIC16F1938-ISS.pdf
(10 pages)
Specifications of PIC16F1938-I/SO
Core Size
8-Bit
Program Memory Size
28KB (16K x 14)
Core Processor
PIC
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
25
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Controller Family/series
PIC16F
Eeprom Memory Size
256Byte
Ram Memory Size
1024Byte
Cpu Speed
32MHz
No. Of Timers
5
Interface
EUSART, I2C, SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F1938-I/SO
Manufacturer:
MITSUMI
Quantity:
12 000
Part Number:
PIC16F1938-I/SO
Manufacturer:
MICROCHI
Quantity:
20 000
- PIC16F722-ISS PDF datasheet
- PIC16LF1933-ISS PDF datasheet #2
- PIC16LF1933-ISS PDF datasheet #3
- PIC16F1938-ISS PDF datasheet #4
- Current page: 370 of 508
- Download datasheet (5Mb)
PIC16F193X/LF193X
BCF
Syntax:
Operands:
Operation:
Status Affected:
Description:
BRA
Syntax:
Operands:
Operation:
Status Affected:
Description:
BRW
Syntax:
Operands:
Operation:
Status Affected:
Description:
BSF
Syntax:
Operands:
Operation:
Status Affected:
Description:
DS41364D-page 370
Relative Branch
[ label ] BRA label
[ label ] BRA $+k
-256 label - PC + 1 255
-256 k 255
(PC) + 1 + k PC
None
Add the signed 9-bit literal ‘k’ to the
PC. Since the PC will have incre-
mented to fetch the next instruction,
the new address will be PC + 1 + k.
This instruction is a two-cycle instruc-
tion. This branch has a limited range.
Bit Clear f
[ label ] BCF
0 f 127
0 b 7
0 (f<b>)
None
Bit ‘b’ in register ‘f’ is cleared.
Relative Branch with W
[ label ] BRW
None
(PC) + (W) PC
None
Add the contents of W (unsigned) to
the PC. Since the PC will have incre-
mented to fetch the next instruction,
the new address will be PC + 1 + (W).
This instruction is a two-cycle instruc-
tion.
Bit Set f
[ label ] BSF
0 f 127
0 b 7
1 (f<b>)
None
Bit ‘b’ in register ‘f’ is set.
f,b
f,b
Preliminary
BTFSC
Syntax:
Operands:
Operation:
Status Affected:
Description:
BTFSS
Syntax:
Operands:
Operation:
Status Affected:
Description:
Bit Test f, Skip if Clear
[ label ] BTFSC f,b
0 f 127
0 b 7
skip if (f<b>) = 0
None
If bit ‘b’ in register ‘f’ is ‘1’, the next
instruction is executed.
If bit ‘b’, in register ‘f’, is ‘0’, the next
instruction is discarded, and a NOP is
executed instead, making this a
2-cycle instruction.
Bit Test f, Skip if Set
[ label ] BTFSS f,b
0 f 127
0 b < 7
skip if (f<b>) = 1
None
If bit ‘b’ in register ‘f’ is ‘0’, the next
instruction is executed.
If bit ‘b’ is ‘1’, then the next
instruction is discarded and a NOP is
executed instead, making this a
2-cycle instruction.
2009 Microchip Technology Inc.
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