PIC24F16KA102-I/SS Microchip Technology, PIC24F16KA102-I/SS Datasheet - Page 112

IC PIC MCU FLASH 16K 28-SSOP

PIC24F16KA102-I/SS

Manufacturer Part Number
PIC24F16KA102-I/SS
Description
IC PIC MCU FLASH 16K 28-SSOP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr

Specifications of PIC24F16KA102-I/SS

Program Memory Type
FLASH
Program Memory Size
16KB (5.5K x 24)
Package / Case
28-SSOP
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
24
Eeprom Size
512 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC24F
Core
PIC
Data Bus Width
16 bit
Data Ram Size
1.5 KB
Interface Type
I2C/IrDA/SPI/UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
24
Number Of Timers
3
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM240001
Minimum Operating Temperature
- 40 C
On-chip Adc
9-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MA240017 - MODULE PLUG-IN PIC24F16KA102 PIM
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
PIC24F16KA102 FAMILY
11.1.1
In addition to the PORT, LAT and TRIS registers for
data control, each port pin can also be individually
configured for either digital or open-drain output. This is
controlled by the Open-Drain Control register, ODCx,
associated with each port. Setting any of the bits
configures the corresponding pin to act as an
open-drain output.
The maximum open-drain voltage allowed is the same
as the maximum V
11.2
The use of the AD1PCFG and TRIS registers control
the operation of the A/D port pins. The port pins that are
desired
corresponding TRIS bit set (input). If the TRIS bit is
cleared (output), the digital output level (V
will be converted.
When reading the PORT register, all pins configured as
analog input channels will read as cleared (a low level).
Analog levels on any pin that is defined as a digital
input (including the ANx pins) may cause the input
buffer to consume current that exceeds the device
specifications.
11.2.1
One instruction cycle is required between a port
direction change or port write operation and a read
operation of the same port. Typically, this instruction
would be a NOP.
11.3
The input change notification function of the I/O ports
allows the PIC24F16KA102 family of devices to
generate interrupt requests to the processor in
response to a change of state on selected input pins.
This feature is capable of detecting input change of
states even in Sleep mode, when the clocks are
EXAMPLE 11-1:
DS39927B-page 110
MOV
MOV
NOP;
BTSS
Equivalent ‘C’ Code
TRISB = 0xFF00;
NOP();
if(PORTBbits.RB13 == 1)
{
}
0xFF00, W0;
W0, TRISBB;
PORTB, #13;
Configuring Analog Port Pins
Input Change Notification
as
OPEN-DRAIN CONFIGURATION
I/O PORT WRITE/READ TIMING
analog
IH
specification.
PORT WRITE/READ EXAMPLE
inputs
//Configure PORTB<15:8> as inputs and PORTB<7:0> as outputs
//Delay 1 cycle
//Next Instruction
//Configure PORTB<15:8> as inputs and PORTB<7:0> as outputs
//Delay 1 cycle
// execute following code if PORTB pin 13 is set.
must
have
OH
or V
their
Preliminary
OL
)
disabled. Depending on the device pin count, there are
up to 23 external signals (CN0 through CN22) that may
be selected (enabled) for generating an interrupt
request on a change of state.
There are six control registers associated with the CN
module. The CNEN1 and CNEN2 registers contain the
interrupt enable control bits for each of the CN input
pins. Setting any of these bits enables a CN interrupt
for the corresponding pins.
Each CN pin also has a weak pull-up/pull-down
connected to it. The pull-ups act as a current source
that is connected to the pin and the pull-downs act as a
current sink to eliminate the need for external resistors
when push button or keypad devices are connected.
On any pin, only the pull-up resistor or the pull-down
resistor should be enabled, but not both of them. If the
push button or the keypad is connected to V
the pull-down, or if they are connected to V
the pull-up resistors. The pull-ups are enabled
separately using the CNPU1 and CNPU2 registers,
which contain the control bits for each of the CN pins.
Setting any of the control bits enables the weak
pull-ups for the corresponding pins. The pull-downs are
enabled separately using the CNPD1 and CNPD2
registers, which contain the control bits for each of the
CN pins. Setting any of the control bits enables the
weak pull-downs for the corresponding pins.
When the internal pull-up is selected, the pin uses V
as the pull-up source voltage. When the internal
pull-down is selected, the pins are pulled down to V
by an internal resistor. Make sure that there is no
external pull-up source/pull-down sink when the
internal pull-ups/pull-downs are enabled.
Note:
Pull-ups and pull-downs on change
notification
disabled
configured as a digital output.
whenever
© 2009 Microchip Technology Inc.
pins
should
the port
always
DD
SS
, enable
, enable
pin
be
DD
SS
is

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