PIC16F818-I/P Microchip Technology, PIC16F818-I/P Datasheet

IC MCU FLASH 1KX14 18-DIP

PIC16F818-I/P

Manufacturer Part Number
PIC16F818-I/P
Description
IC MCU FLASH 1KX14 18-DIP
Manufacturer
Microchip Technology
Series
PIC® 16Fr

Specifications of PIC16F818-I/P

Program Memory Type
FLASH
Program Memory Size
1.75KB (1K x 14)
Package / Case
18-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
I2C/SPI/SSP
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
16
Number Of Timers
3
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014
Minimum Operating Temperature
- 40 C
On-chip Adc
5-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
ACICE0202 - ADAPTER MPLABICE 18P 300 MILAC164010 - MODULE SKT PROMATEII DIP/SOIC
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16F818-I/P
Manufacturer:
Microchip Technology
Quantity:
295
M
PICmicro™
Mid-Range MCU Family
Reference Manual
1997 Microchip Technology Inc.
December 1997 /DS33023A

PIC16F818-I/P Summary of contents

Page 1

... Microchip Technology Inc. M PICmicro™ Mid-Range MCU Family Reference Manual December 1997 /DS33023A ...

Page 2

... Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies. No licenses are conveyed, implicitly or otherwise, under any intellectual prop- erty rights.” ...

Page 3

... Related Application Notes ..............................................................................................................................3-17 Revision History .............................................................................................................................................3-18 SECTION 4. ARCHITECTURE Introduction .......................................................................................................................................................4-2 Clocking Scheme/Instruction Cycle ..................................................................................................................4-5 Instruction Flow/Pipelining ................................................................................................................................4-6 I/O Descriptions ................................................................................................................................................4-7 Design Tips ....................................................................................................................................................4-12 Related Application Notes ..............................................................................................................................4-13 Revision History .............................................................................................................................................4-14 1997 Microchip Technology Inc. Table of Contents PAGE 1-1 2-1 3-1 4-1 DS00097D-page iii ...

Page 4

... Introduction .......................................................................................................................................................8-2 Control Registers ..............................................................................................................................................8-5 Interrupt Latency ............................................................................................................................................8-10 INT and External Interrupts ............................................................................................................................8-10 Context Saving During Interrupts ...................................................................................................................8-11 Initialization .....................................................................................................................................................8-14 Design Tips ....................................................................................................................................................8-16 Related Application Notes ..............................................................................................................................8-17 Revision History .............................................................................................................................................8-18 DS00097D-page iv Table of Contents M PAGE 5-1 6-1 7-1 8-1 1997 Microchip Technology Inc. ...

Page 5

... SECTION 10. PARALLEL SLAVE PORT Introduction .....................................................................................................................................................10-2 Control Register .............................................................................................................................................10-3 Operation ........................................................................................................................................................10-4 Operation in Sleep Mode ................................................................................................................................10-5 Effect of a Reset .............................................................................................................................................10-5 PSP Waveforms .............................................................................................................................................10-5 Design Tips ....................................................................................................................................................10-6 Related Application Notes ..............................................................................................................................10-7 Revision History .............................................................................................................................................10-8 1997 Microchip Technology Inc. Table of Contents PAGE 9-1 10-1 DS00097D-page v ...

Page 6

... SECTION 14. COMPARE/CAPTURE/PWM (CCP) Introduction .....................................................................................................................................................14-2 Control Register .............................................................................................................................................14-3 Capture Mode .................................................................................................................................................14-4 Compare Mode ...............................................................................................................................................14-6 PWM Mode .....................................................................................................................................................14-8 Initialization ...................................................................................................................................................14-12 Design Tips ..................................................................................................................................................14-15 Related Application Notes ............................................................................................................................14-17 Revision History ...........................................................................................................................................14-18 DS00097D-page vi Table of Contents M PAGE 11-1 12-1 13-1 14-1 1997 Microchip Technology Inc. ...

Page 7

... USART Baud Rate Generator (BRG) .............................................................................................................18-5 USART Asynchronous Mode .........................................................................................................................18-8 USART Synchronous Master Mode .............................................................................................................18-15 USART Synchronous Slave Mode ...............................................................................................................18-19 Initialization ...................................................................................................................................................18-21 Design Tips ..................................................................................................................................................18-22 Related Application Notes ............................................................................................................................18-23 Revision History ...........................................................................................................................................18-24 1997 Microchip Technology Inc. Table of Contents 2 C Bus ........................................................................................................17-56 PAGE 15-1 16-1 17-1 ...

Page 8

... A/D Accuracy/Error .......................................................................................................................................21-13 Effects of a RESET ......................................................................................................................................21-13 Use of the CCP Trigger ................................................................................................................................21-14 Connection Considerations ..........................................................................................................................21-14 Transfer Function .........................................................................................................................................21-14 Initialization ...................................................................................................................................................21-15 Design Tips ..................................................................................................................................................21-16 Related Application Notes ............................................................................................................................21-17 Revision History ...........................................................................................................................................21-18 DS00097D-page viii Table of Contents M PAGE 19-1 20-1 21-1 1997 Microchip Technology Inc. ...

Page 9

... Revision History ...........................................................................................................................................23-20 SECTION 24. SLOPE A/D Introduction .....................................................................................................................................................24-2 Control Registers ............................................................................................................................................24-3 Conversion Process .......................................................................................................................................24-6 Other Analog Modules ..................................................................................................................................24-12 Calibration Parameters .................................................................................................................................24-13 Design Tips ..................................................................................................................................................24-14 Related Application Notes ............................................................................................................................24-15 Revision History ...........................................................................................................................................24-16 1997 Microchip Technology Inc. Table of Contents PAGE 22-1 23-1 24-1 DS00097D-page ix ...

Page 10

... Programmer ...................................................................................................................................................28-6 Programming Environment .............................................................................................................................28-6 Other Benefits ................................................................................................................................................28-7 Field Programming of PICmicro OTP MCUs ..................................................................................................28-8 Field Programming of FLASH PICmicros .....................................................................................................28-10 Design Tips ..................................................................................................................................................28-12 Related Application Notes ............................................................................................................................28-13 Revision History ...........................................................................................................................................28-14 DS00097D-page x Table of Contents M PAGE 25-1 26-1 27-1 28-1 1997 Microchip Technology Inc. ...

Page 11

... Example LCD Timing Waveforms and Requirements ..................................................................................30-40 Related Application Notes ............................................................................................................................30-41 Revision History ...........................................................................................................................................30-42 SECTION 31. DEVICE CHARACTERISTICS Introduction .....................................................................................................................................................31-2 Characterization vs. Electrical Specification ...................................................................................................31-2 DC and AC Characteristics Graphs and Tables .............................................................................................31-2 Revision History ...........................................................................................................................................31-22 1997 Microchip Technology Inc. Table of Contents PAGE 29-1 30-1 31-1 DS00097D-page xi ...

Page 12

... Revision History ...........................................................................................................................................32-16 SECTION 33. CODE DEVELOPMENT Revision History .............................................................................................................................................33-2 SECTION 34. APPENDIX Overview ...............................................................................................................................................34-2 List of LCD Glass Manufacturers ................................................................................................................. 34-11 Device Enhancement ...................................................................................................................................34-13 Revision History ........................................................................................................................................... 34-19 SECTION 35. GLOSSARY Revision History ...........................................................................................................................................35-14 DS00097D-page xii Table of Contents M PAGE 32-1 33-1 34-1 35-1 1997 Microchip Technology Inc. ...

Page 13

... Manual Objective ...........................................................................................................1-3 1.3 Device Structure ............................................................................................................1-4 1.4 Development Support ....................................................................................................1-6 1.5 Device Varieties..............................................................................................................1-7 1.6 Style and Symbol Conventions ....................................................................................1-12 1.7 Related Documents .....................................................................................................1-14 1.8 Related Application Notes............................................................................................1-17 1.9 Revision History ...........................................................................................................1-18 1997 Microchip Technology Inc. 1 DS31001A page 1-1 ...

Page 14

... MCU application as well as some traditional 4-bit applications (Base-Line family), dedicated logic replacement and low-end DSP applications (High-End family). These fea- tures and price-performance mix make PICmicro MCUs an attractive solution for most applications. DS31001A-page 1-2 OQ ® 1997 Microchip Technology Inc. ...

Page 15

... The first few Mid-Range devices have minor device variations when compared to this general description. We have tried to describe these variations throughout this manual. Please refer to the specific device data sheet for complete information on the device. 1997 Microchip Technology Inc. Section 1. Introduction 12-bit Instruction Word length 16-bit Instruction Word length ...

Page 16

... Revision “DS31014A” Revision “DS31015A” Revision “DS31016A” Revision “DS31017A” Revision “DS31018A” Revision “DS31019A” Revision “DS31020A” Revision “DS31021A” Revision “DS31022A” Revision “DS31023A” Revision “DS31024A” Revision “DS31025A” Revision “DS31010A” 1997 Microchip Technology Inc. ...

Page 17

... Watchdog Timer 5. Low power mode (Sleep) 6. Internal RC device oscillator 7. In-Circuit Serial Programming™ (ICSP™) 1997 Microchip Technology Inc. Section 1. Introduction Revision “DS31027A” Revision “DS31003A” Revision “DS31003A” Revision “DS31026A” Revision “DS31026A” Revision “DS31002A” Revision “DS31028A” ...

Page 18

... Corporate Support Line Additional avenues of assistance can be found in many Web User Groups including the MIT reflector PIClist. The Microchip web site lists other sites that may be useful references. DS31001A-page 1-6 In-Circuit Emulator “Development “Code Development” 1997 Microchip Technology Inc. ...

Page 19

... Being electrically erasable, these devices can be both erased and reprogrammed without removal from the circuit. A device will have the same specifications whether it is used for proto- type development, pilot programs, or production. 1997 Microchip Technology Inc. Section 1. Introduction 1 DS31001A-page 1-7 ...

Page 20

... Microchip specifications its extended range devices at a more con- EPROM C 4 3.0 - 6.0V LCR LC 2.5 - 6.0V LCR Table 1-1 Extended PIC16LCXXX PIC16LCRXXX PIC16LFXXX ROM Flash 4.5 - 6.0V F 4.5 - 6.0V 3.0 - 6.0V LF 3.0 - 6.0V 2.5 - 6.0V LF 2.0 - 6.0V of 5.5V. New DD 1997 Microchip Technology Inc. ...

Page 21

... Table 1-3: Typical Package Uses Package Type Windowed Plastic DIE 1997 Microchip Technology Inc. Section 1. Introduction Typical Usage Development Mode Production Special Applications, such as those which require minimum board space 1 Table 1-3 ...

Page 22

... An EEPROM device allows its memory to be erased by an electric charge. This means that the system can be designed so that erasure and reprogramming may be performed in-circuit. Since no window is required, the lower cost plastic packages can used for these devices. DS31001A-page 1-10 1997 Microchip Technology Inc. ...

Page 23

... Microchip offers a this unique programming service where a few user-defined locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random or sequential. Serial programming allows each device to have a unique number which can serve as an entry-code, password or ID number. 1997 Microchip Technology Inc. Section 1. Introduction SM ) Programming 1 ...

Page 24

... Note: This is a note in a note box. A caution statement describes a situation that could potentially damage software or equipment. A warning statement describes a situation that could potentially cause personnel harm. provides a description for many “Glossary” section, 1997 Microchip Technology Inc. ...

Page 25

... Format Dxxx Axxx xxx PDxxx Pxxx Legend: xxx: represents a number. 1997 Microchip Technology Inc. Section 1. Introduction section shows all the specifications that are documented for all Comment DC Specification DC Specification for Analog peripherals Timing (AC) Specification Device Programming DC Specification Device Programming Timing (AC) Specifi ...

Page 26

... This document lists Microchip’s third parties, as well as various consultants. 19. DIE Support (DS30258) This document gives information on using Microchip products in DIE form. DS31001A-page 1-14 ® User’s Guide (DS30421) ® User’s Guide (DS30082) -Plus User’s Guide (DS51028) ® -MP User’s Guide (DS30389) 1997 Microchip Technology Inc. ...

Page 27

... Michael Rose, Hüthig 3-7785-2170-5...........................................................................................................German Les Microcontrolleurs PIC et mise en oeuvre Christian Tavernier, Dunod 2-10-002647-X ............................................................................................................French Micontrolleurs PIC a structure RISC C.F. Urbain, Publitronic 2-86661-058-X ............................................................................................................French New Possibilities with the Microchip PIC RIGA ......................................................................................................................... Russian 1997 Microchip Technology Inc. Section 1. Introduction ® 1 LANGUAGE DS31001A-page 1-15 ...

Page 28

... Chinese PIC16C5X/71/84 Development and Design, Part 4 United Tech Electronic Co. Ltd 957-21-1251-1.......................................................................................................... Chinese PIC16C5X/71/84 Development and Design, Part 5 United Tech Electronic Co. Ltd 957-21-1257-0.......................................................................................................... Chinese PIC16C84 MCU Architecture and Software Development ICC Company 957-8716-79-6.......................................................................................................... Chinese DS31001A-page 1-16 LANGUAGE 1997 Microchip Technology Inc. ...

Page 29

... Microchip’s PICmicro MCUs are: Title A Comparison of Low End 8-bit Microcontrollers PIC16C54A EMI Results Continuous Improvement Improving the Susceptibility of an Application to ESD Plastic Packaging and the Effects of Surface Mount Soldering Techniques 1997 Microchip Technology Inc. Section 1. Introduction Application Note # 1 AN520 AN577 AN503 ...

Page 30

... PICmicro MID-RANGE MCU FAMILY 1.9 Revision History Revision A This is the initial released revision of Microchip’s PICmicro MCUs Introduction. DS31001A-page 1-18 1997 Microchip Technology Inc. ...

Page 31

... Internal 4 MHz RC Oscillator .......................................................................................2-13 2.6 Effects of Sleep Mode on the On-chip Oscillator .........................................................2-17 2.7 Effects of Device Reset on the On-chip Oscillator .......................................................2-17 2.8 Design Tips ..................................................................................................................2-18 2.9 Related Application Notes............................................................................................2-19 2.10 Revision History ...........................................................................................................2-20 1997 Microchip Technology Inc. 2 DS31002A page 2-1 ...

Page 32

... The RC mode and the EXTRC with CLKOUT mode have the same functionality. They are named like this to help describe their operation vs. the other oscillator modes. DS31002A-page 2-2 ) cycle. CY “Device Characteristics” section. Table 2-1 and Table 2-2 1997 Microchip Technology Inc. give infor- ). The DD ...

Page 33

... Table 2-2: Selecting the Oscillator Mode for Devices with FOSC2:FOSC0 Configuration bits FOSC2:FOSC0 1997 Microchip Technology Inc. Section 2. Oscillator OSC OSC Feedback Mode Inverter Gain RC — Least expensive solution for device oscillation (only an external resistor and capacitor is required). Most variation in time-base. ...

Page 34

... The PICmicro oscillator design requires the use of a parallel 2-3). OSC1 C1 To internal logic XTAL SLEEP F (2) R OSC2 ( internal logic PIC16CXXX , may be required for AT strip cut crystals typically in the range either before or after the oscillator inverter. (3) (3) 1997 Microchip Technology Inc. ...

Page 35

... The peak-to-peak voltage of the oscillator waveform can be quite low (less than 50% of device V tered (refer to DD Figure 2-2: Example Oscillator / Resonator Start-up Characteristics Maximum V 1997 Microchip Technology Inc. Section 2. Oscillator , the oscillator will start its oscillations. The time SS Figure 2-1) Figure ...

Page 36

... MHz Resonators used: Panasonic EFO-A455K04B Murata Erie CSA2.00MG Murata Erie CSA4.00MG Murata Erie CSA8.00MT Murata Erie CSA16.00MX TBD Figure 2-1, the connection to Table 2-4. Each device’s data ( 100 TBD 0.3% 0.5% 0.5% 0.5% 0.5% TBD 1997 Microchip Technology Inc. ...

Page 37

... HS mode as well as XT mode to avoid overdriving crystals with low drive level specification. Since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external compo- nents or verify oscillator performance. 1997 Microchip Technology Inc. Section 2. Oscillator (1) C1 ...

Page 38

... DS31002A-page 2-8 1997 Microchip Technology Inc. ...

Page 39

... and scope probe was 10 pF capacitor may actually be called for. The output signal should not be clipping or squashed. Overdriving the crystal can also lead to the circuit jumping to a higher harmonic level or even crystal damage. 1997 Microchip Technology Inc. Section 2. Oscillator parameter specification ...

Page 40

... Note 1: A resistor to ground may be used to reduce system noise. DS31002A-page 2-10 combination will assure this is the maximum DD clock from OSC1 external system (1) OSC2 Open This may increase system current. is usually good). An easy way DD that the DD and PIC16CXXX 1997 Microchip Technology Inc. ...

Page 41

... The 330 k resistors provide the negative feedback to bias the inverters in their linear region. Figure 2-5: External Series Resonant Crystal Oscillator Circuit When the device is clocked from an external clock source (as in the microcontroller’s oscillator must be configured for LP mode 1997 Microchip Technology Inc. Section 2. Oscillator +5V To Other Devices ...

Page 42

... D032 section). The time required for the RC to start oscillating depends on many fac- ) and capacitor EXT between 3 k and 100 k . Internal clock PIC16CXXX = 0 pF), we recommend EXT for given EXT EXT , C , and EXT EXT in and D042 in the “Electrical 1997 Microchip Technology Inc. ...

Page 43

... OSCCAL is used to remove process variation from the internal RC oscillator of the device. The OSCCAL value should not be modified from the Microchip supplied value, and all timing critical functions should be adjusted by the application software. 1997 Microchip Technology Inc. Section 2. Oscillator R/W-1 R/W-1 ...

Page 44

... CALFST = 0 CALSLW = 0 CAL3:CAL0 = Fh CAL3:CAL0 = 0h CALFST = 0 CALFST = 0 CALSLW = 0 CALSLW = 0 CAL3:CAL0 Trim Window CAL3:CAL0 = 0000 One of the 16 possible calibration points = 5V See X-axis CAL3:CAL0 = Fh CALFST = 1 CALSLW = x (fastest frequency) Figure 2-9, and Internal RC Frequency at device reset CALFST = 0 CALFLW = 0 CAL3:CAL0 = 7h CAL3:CAL0 = 1111 1997 Microchip Technology Inc. ...

Page 45

... MHz Figure 2-10: CALSLW Negative Internal RC Oscillator Frequency Offset > 4 MHz 4 MHz 1.5% (@ 5V, 25˚C) CAL3:CAL0 = 0000 1997 Microchip Technology Inc. Section 2. Oscillator CAL3:CAL0 Trim Window CAL3:CAL0 = 0000 One of the 16 possible CAL3:CAL0 calibration points CAL3:CAL0 Trim Window One of the 16 possible CAL3:CAL0 calibration points ...

Page 46

... This value then needs to be written to a port or shifted out serially, so that the value can be written down and programmed into the calibration location. DS31002A-page 2-16 Table 2-5 shows the location of the calibration value depending on the size Calibration Value Location 1FFh 3FFh 7FFh FFFh 1FFFh 1997 Microchip Technology Inc. ...

Page 47

... BOR). The PWRT is designed to keep the part in RESET while the power supply sta- bilizes. With these two timers on-chip, most applications need no external reset circuitry. For additional information on reset operation, see the 1997 Microchip Technology Inc. Section 2. Oscillator OSC1 Pin ...

Page 48

... If the frequency of the device does not matter, you can continue to use the device. If the frequency of the device does matter, you can purchase a new windowed device, or follow the suggestion in subsection DS31002A-page 2-18 to aid in the selection of C2 (may need to be higher) Rs (may be needed) 2.5.1 “Clock Out.” rise DD 2.3 “Crystal Oscillators / 1997 Microchip Technology Inc. ...

Page 49

... Base-Line, or High-End families), but the concepts are pertinent, and could be used (with modification and possible limitations). The current application notes related to the oscillator are: Title PIC16/17 Oscillator Design Guide Low Power Design using PIC16/17 1997 Microchip Technology Inc. Section 2. Oscillator Application Note # DS31002A-page 2-19 AN588 AN606 ...

Page 50

... PICmicro MID-RANGE MCU FAMILY 2.10 Revision History Revision A This is the initial released revision of the PICmicro oscillators description. DS31002A-page 2-20 1997 Microchip Technology Inc. ...

Page 51

... Power-on Reset (POR), Power-up Timer (PWRT), Oscillator Start-up Timer (OST), Brown-out Reset (BOR), and Parity Error Reset (PER).................................................3-4 3.3 Registers and Status Bit Values ...................................................................................3-10 3.4 Design Tips ..................................................................................................................3-16 3.5 Related Application Notes............................................................................................3-17 3.6 Revision History ...........................................................................................................3-18 1997 Microchip Technology Inc. Section 3. Reset 3 DS31003A page 3-1 ...

Page 52

... DS31003A-page 3-2 Table 3-2. These bits are used in software to determine the nature Table 3-4 for a full description of the reset states of all registers. in the “Electrical Specifications” section for pulse width specification. Figure 3-1. This block diagram 1997 Microchip Technology Inc. ...

Page 53

... In some devices, this pin may be configured as a general purpose Input. 4: The early PICmicro devices have the configuration bit defined as PWRTE = 1 is enabled, while all other devices the configuration bit is defined as PWRTE = 0 is enabled. 1997 Microchip Technology Inc. Section 3. Reset (2) ...

Page 54

... The diode, D, helps discharge the DD powers down MCLR PIC16CXXX C is recommended to ensure that the voltage drop across R does not rise is detected. To take advantage of as shown in Figure 3-2. This DD in the “Electrical Spec- Power-up) DD level on the MCLR/V pin 1997 Microchip Technology Inc. ...

Page 55

... Figure 3-4: Oscillator Start-up Time Tosc1 = time for the crystal oscillator to react to an oscillation level detectable by the Oscillator Start-up Timer (OST 1024T OST 1997 Microchip Technology Inc. Section 3. Reset parameter 33 in the “Electrical Specifications” to rise to an acceptable level. The power-up timer enable DD ...

Page 56

... OST TIME-OUT INTERNAL RESET DS31003A-page 3-6 depict time-out sequences. Power-up Timer Enabled Disabled 1024T 1024T OSC OSC ( — T PWRT T OST Figure 3-5, (Figure 3-7). Figure 3-5 through Wake-up Brown-out Reset from SLEEP 1024T 1024T OSC OSC ( — 1997 Microchip Technology Inc. ...

Page 57

... Time-out Sequence on Power-up (MCLR not Tied MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET Figure 3-8: Slow Rise Time (MCLR Tied MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET 1997 Microchip Technology Inc. Section 3. Reset ): Case PWRT T OST ): Case PWRT T OST ) DD 5V ...

Page 58

... BV . The Power-up Timer will now be invoked DD DD drops below the Power-up Timer will again start time delay. DD will hold the device in the reset state. This < the “Electrical Spec- parameter 35. The chip will while the Power-up DD Figure 3 1997 Microchip Technology Inc. ...

Page 59

... Note 1: This brown-out circuit is less expensive, albeit less accurate. Transistor Q1 turns off when Internal Brown-out Reset circuitry should be disabled when using this circuit. 3: Resistors should be adjusted for the characteristics of the transistor. 1997 Microchip Technology Inc. Section 3. Reset are two examples of external circuitry that may be implemented ...

Page 60

... POR or a BOR will read as a '1'. DS31003A-page 3-10 ( Power-on Reset Illegal set on POR Illegal set on POR Brown-out Reset (2) WDT Reset 0 1 (2) WDT Wake- (2) MCLR reset during normal operation u u (2) MCLR reset during SLEEP unknown unimplemented bit, reads as ‘0’. Condition 1997 Microchip Technology Inc. ...

Page 61

... Note 1: When the wake-up is due to an interrupt and global enable bit, GIE, is set the PC is loaded with the interrupt vector (0004h) after execution of PC+ status bit is not implemented, that bit will be read as ‘0’. 1997 Microchip Technology Inc. Section 3. Reset Program ...

Page 62

... ---u uuuu ---- --uu uuuu uuuu ---- ---u uuuu uuuu 1997 Microchip Technology Inc. ...

Page 63

... When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table 3-3 for reset value for specific condition. 1997 Microchip Technology Inc. Section 3. Reset MCLR Reset during: - normal operation - SLEEP or ...

Page 64

... R = Readable bit U = Unimplemented bit, read as ‘0’ Note: Not all bits may be implemented. DS31003A-page 3-14 U-0 U-0 U-0 U-0 — — — — Writable bit u = unchanged bit - n = Value at POR reset R/W-0 R/W-0 R/W-0 PER POR BOR bit 0 1997 Microchip Technology Inc. ...

Page 65

... For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register. Legend R = Readable bit U = Unimplemented bit, read as ‘0’ 1997 Microchip Technology Inc. Section 3. Reset R/W-0 R-1 R-1 R/W-x ...

Page 66

... The background light causes the device to power- different state than would typically be seen in a device where no light is present. In most cases all the General Purpose RAM and Special Function Registers were not initialized properly. DS31003A-page 3-16 parameter 35 specifies the pulse width required to cause a reset. (Appendix C), 1997 Microchip Technology Inc. ...

Page 67

... Base-Line, or High-End families), but the concepts are pertinent, and could be used (with modification and possible limitations). The current application notes related to Resets are: Title Power-up Trouble Shooting Power-up Considerations 1997 Microchip Technology Inc. Section 3. Reset Application Note # AN607 AN522 ...

Page 68

... PICmicro MID-RANGE MCU FAMILY 3.6 Revision History Revision A This is the initial released revision of the Reset description. DS31003A-page 3-18 1997 Microchip Technology Inc. ...

Page 69

... This section of the manual contains the following major topics: 4.1 Introduction ....................................................................................................................4-2 4.2 Clocking Scheme/Instruction Cycle ...............................................................................4-5 4.3 Instruction Flow/Pipelining .............................................................................................4-6 4.4 I/O Descriptions .............................................................................................................4-7 4.5 Design Tips ..................................................................................................................4-12 4.6 Related Application Notes............................................................................................4-13 4.7 Revision History ...........................................................................................................4-14 1997 Microchip Technology Inc. 4 DS31004A page 4-1 ...

Page 70

... This 2:1 ratio is generalized and dependent on the application code. Since each instruction may take multiple bytes, there is no assurance that each location is a valid instruction. DS31004A-page 4-2 Harvard Program CPU Memory 14 von-Neumann Program and CPU Data 8 Memory 1997 Microchip Technology Inc. ...

Page 71

... One is the SLEEP instruction which places the device into the lowest power use mode. The other is the CLRWDT instruction which verifies the chip is operating properly by preventing the on-chip Watchdog Timer (WDT) from overflowing and resetting the device. 1997 Microchip Technology Inc. Section 4. Architecture , while the execution takes another T CY ...

Page 72

... RD2 RD3 RD4 RD5 RD6 RD7 PORTE RE0 RE1 RE2 RE3 RE4 RE5 RE6 RE7 PORTF RF0 RF1 RF2 RF3 RF4 RF5 RF6 RF7 PORTG RG0 RG1 RG2 RG3 RG4 RG5 RG6 RG7 General Purpose I/O (Note 3) 1997 Microchip Technology Inc. ...

Page 73

... Q4. The clocks and instruction execution flow are illustrated in Example 4-1. Figure 4-3: Clock/Instruction Cycle OSC1 OSC2/CLKOUT (RC mode) Fetch INST (PC) Execute INST (PC-1) 1997 Microchip Technology Inc. Section 4. Architecture PC+1 Fetch INST (PC+1) Execute INST (PC) Fetch INST (PC+2) Execute INST (PC+1) Figure 4-3, and ...

Page 74

... CY 4, instruction four is flushed (executed as a NOP) and Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch 4 (Example 4-1). 1, the first instruc the second instruction exe needs CY 5, instruction five is executed and Flush Fetch SUB_1 Execute SUB_1 Fetch SUB_1 + 1 1997 Microchip Technology Inc. ...

Page 75

... ST = Schmitt Trigger input with CMOS levels SM = SMBus compatible input. An external resistor is required if this pin is used as an output NPU = N-channel pull-up No-P diode = No P-diode input P = Power 1997 Microchip Technology Inc. Section 4. Architecture Description Analog Input Channels Analog Power Analog Ground LCD Voltage Generation ...

Page 76

... Parallel Slave Port for interfacing to a microprocessor port. These pins have TTL input buffers when PSP module is enabled. PORTA is a bi-directional I/O port. RA4 is an open drain when configured as output. CMOS = CMOS compatible input or output PU = Weak internal pull- Analog input or output output L = LCD Driver 1997 Microchip Technology Inc. ...

Page 77

... SM = SMBus compatible input. An external resistor is required if this pin is used as an output NPU = N-channel pull-up No-P diode = No P-diode input P = Power 1997 Microchip Technology Inc. Section 4. Architecture Description PORTB is a bi-directional I/O port. PORTB can be software pro- grammed for internal weak pull-ups on all inputs. Interrupt on change pin. ...

Page 78

... Timer0 external clock input Timer1 external clock input Timer1 oscillator output Timer1 oscillator input USART Asynchronous Transmit (See related RX) CMOS = CMOS compatible input or output PU = Weak internal pull- Analog input or output output L = LCD Driver 2 C mode interface 2 C interface 1997 Microchip Technology Inc. ...

Page 79

... ST = Schmitt Trigger input with CMOS levels SM = SMBus compatible input. An external resistor is required if this pin is used as an output NPU = N-channel pull-up No-P diode = No P-diode input P = Power 1997 Microchip Technology Inc. Section 4. Architecture Description LCD Voltage LCD Voltage LCD Voltage LCD Voltage Generation Analog High Voltage Reference input ...

Page 80

... PICmicro MID-RANGE MCU FAMILY 4.5 Design Tips No related design tips at this time. DS31004A-page 4-12 1997 Microchip Technology Inc. ...

Page 81

... Base-Line, or High-End families), but the concepts are pertinent, and could be used (with modification and possible limitations). The current application notes related to Architecture are: Title No related application notes at this time. 1997 Microchip Technology Inc. Section 4. Architecture Application Note # 4 DS31004A-page 4-13 ...

Page 82

... PICmicro MID-RANGE MCU FAMILY 4.7 Revision History Revision A This is the initial released revision of the PICmicro’s Architecture description. DS31004A-page 4-14 1997 Microchip Technology Inc. ...

Page 83

... Instruction Clock ............................................................................................................5-4 5.5 Arithmetic Logical Unit (ALU).........................................................................................5-5 5.6 STATUS Register ...........................................................................................................5-6 5.7 OPTION_REG Register .................................................................................................5-8 5.8 PCON Register ..............................................................................................................5-9 5.9 Design Tips ..................................................................................................................5-10 5.10 Related Application Notes............................................................................................5-11 5.11 Revision History ...........................................................................................................5-12 1997 Microchip Technology Inc. 5 DS31005A page 5-1 ...

Page 84

... STATUS register). The result of some instructions force status bits to a value depend- ing on the state of the result. The machine codes that the CPU recognizes are show in mnemonics that the MPASM uses to generate these codes). DS31005A-page 5-2 Table 5-1 (as well as the instruction 1997 Microchip Technology Inc. ...

Page 85

... If this instruction is executed on the TMR0 register (and, where applicable 1), the prescaler will be cleared if assigned to the Timer0 Module Program Counter (PC) is modifi conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 1997 Microchip Technology Inc. Section 5. CPU and ALU 14-Bit Instruction Word Cycles ...

Page 86

... Q cycles (Q1-Q4). The Q cycle time is the same CY ). The Q cycles provide the timing/designation for the OSC ) can be generalized as for destination for destination 7-bit file register address b = 3-bit bit address f = 7-bit file register address k = 8-bit immediate value k = 11-bit immediate value 1997 Microchip Technology Inc. ...

Page 87

... Carry (DC), and Zero (Z) bits in the STATUS register. The C and DC bits operate as a borrow bit and a digit borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples. 1997 Microchip Technology Inc. Section 5. CPU and ALU 8-bit literal (from instruction word) ...

Page 88

... Note 2: The C and DC bits operate as a borrow and digit borrow bit, respectively, in subtrac- tion. DS31005A-page 5-6 Figure 5-1, contains the arithmetic status of the ALU, the RESET Figure 6-5: “Register File Map” section). in the “Mem- Table 5-1. 1997 Microchip Technology Inc. ...

Page 89

... For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register. Legend R = Readable bit U = Unimplemented bit, read as ‘0’ 1997 Microchip Technology Inc. Section 5. CPU and ALU R/W-0 R-1 R-1 ...

Page 90

... To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer. DS31005A-page 5-8 R/W-1 R/W-1 R/W-1 R/W-1 T0CS T0SE PSA WDT Rate 128 W = Writable bit - n = Value at POR reset R/W-1 R/W-1 PS2 PS1 PS0 bit 0 1997 Microchip Technology Inc. ...

Page 91

... BOR: Brown-out Reset Status bit Brown-out Reset occurred Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Legend R = Readable bit U = Unimplemented bit, read as ‘0’ 1997 Microchip Technology Inc. Section 5. CPU and ALU U-0 U-0 U-0 R/W-0 — — ...

Page 92

... STATUS register is the destination for an instruction that affects the Z, DC bits, the write to these bits is disabled. These bits are set or cleared based on device logic. Therefore, to modify bits in the STATUS register it is recommended to use the BCF and BSF instructions. DS31005A-page 5-10 1997 Microchip Technology Inc. ...

Page 93

... Implementation of Fast Fourier Transforms Tone Generation Servo Control Brushless Motor Implementation of the Data Encryption Standard using the PIC17C42 PIC16C5X / PIC16CXX Utility Math Routines Real Time Operating System for PIC16/17 1997 Microchip Technology Inc. Section 5. CPU and ALU Application Note # AN617 AN575 AN616 ...

Page 94

... PICmicro MID-RANGE MCU FAMILY 5.11 Revision History Revision A This is the initial released revision of the CPU and ALU description. DS31005A-page 5-12 1997 Microchip Technology Inc. ...

Page 95

... This section of the manual contains the following major topics: 6.1 Introduction ....................................................................................................................6-2 6.2 Program Memory Organization......................................................................................6-2 6.3 Data Memory Organization ............................................................................................6-8 6.4 Initialization ..................................................................................................................6-14 6.5 Design Tips ..................................................................................................................6-16 6.6 Related Application Notes............................................................................................6-17 6.7 Revision History ...........................................................................................................6-18 1997 Microchip Technology Inc. 6 DS31006A page 6-1 ...

Page 96

... For devices that have less than 8K words, accessing a location above the physically implemented address will cause a wraparound. That is 4K-word device accessing 17FFh actually addresses 7FFh. 2K-word devices (or less) do not require paging. DS31006A-page 6-2 Figure 6-1 shows the program memory map as well 1997 Microchip Technology Inc. ...

Page 97

... Section 6. Memory Organization Figure 6-1: Architectural Program Memory Map and Stack 6K 8K Note 1: Not all devices implement the entire program memory space 2: Calibration Data may be programmed into program memory locations. 1997 Microchip Technology Inc. PCLATH PCL PC<12:0> PC<12:8> CALL, RETURN 13 RETFIE, RETLW ...

Page 98

... Note: For windowed devices, write down all calibration values BEFORE erasing. This allows the device’s calibration values to be restored when the device is re-pro- grammed. When possible writing the values on the package is recommended. DS31006A-page 6-4 1997 Microchip Technology Inc. ...

Page 99

... Situation 4 - RETURN, RETFIE, or RETLW Instruction Note: PCLATH is never updated with the contents of PCH. 1997 Microchip Technology Inc. PCH). Situation 2 shows how the PC is loaded during PCH). Situation 3 shows how the PC is loaded during a PCH), with the PC loaded (PUSHed) onto the Top of Stack. ...

Page 100

... Note 2: There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW, and RETFIE instructions, or the vectoring to an interrupt address. DS31006A-page 6-6 Figure 6-3. STACK Push1 Push9 Top of STACK Push2 Push10 Push3 Push4 Push5 Push6 Push7 Push8 1997 Microchip Technology Inc. ...

Page 101

... Example 6-1: Call of a Subroutine in Page1 from Page0 ORG 0x500 BSF PCLATH,3 CALL SUB1_P1 : : ORG 0x900 SUB1_P1: : RETURN 1997 Microchip Technology Inc. (Figure 6-2). When doing a CALL or (Figure 6-2). When one of the return instruc- ; Select Page1 (800h-FFFh) ; Call subroutine in Page1 (800h-FFFh called subroutine Page1 (800h-FFFh) ; ...

Page 102

... Some SFRs are initialized by a Power-on Reset and other resets, while other SFRs are unaffected. Note: The Special Function Register (SFR) Area may have General Purpose Registers (GPRs) mapped in these locations. The register file can be accessed either directly, or using the File Select Register FSR, indirectly. DS31006A-page 6-8 Figure 6-5 shows 1997 Microchip Technology Inc. ...

Page 103

... As with all the figures, tables, and specifications presented in this reference guide, verify the details with the device spe- cific data sheet. Figure 6-4: Direct Addressing RP1 RP0 bank select location select 1997 Microchip Technology Inc. Indirect (IRP ...

Page 104

... General Purpose (3) 16Fh Registers 1EFh 170h Mapped in 1F0h Bank0 (4) 17Fh 70h - 7Fh 1FFh (5) Bank3 1997 Microchip Technology Inc. ...

Page 105

... Not all locations may be implemented. Unimplemented locations will read as ’0’. 4: These locations are unimplemented in Bank1. Access to these unimplemented locations will access the corresponding Bank0 register. 1997 Microchip Technology Inc. shows the register file memory map of some 18-pin devices. File File ...

Page 106

... IRP bit (STATUS<7>) with the 8-bit FSR register, as shown in Figure 6-7: Indirect Addressing DS31006A-page 6-12 Instruction Executed Opcode Address 9 File Address = INDF Address != 0 Address = 0h RP1:RP0 9 9 Instruction 2 7 Fetched Opcode File IRP Figure 6-7 shows the operation of Figure 6-8. RAM FSR 1997 Microchip Technology Inc. ...

Page 107

... USART transmit register (TXREG). The starting address of the block of data to be transmitted could easily be modified by the program. Example 6-2: Indirect Addressing BCF MOVLW MOVWF NEXT CLRF INCF BTFSS GOTO CONTINUE : 1997 Microchip Technology Inc. Indirect Addressing 7 IRP bank select 00h Data Memory 7Fh Bank1 ...

Page 108

... STATUS, RP0 : BCF STATUS, RP0 : MOVLW 0x60 XORWF STATUS BCF STATUS, RP0 : BCF STATUS, RP1 DS31006A-page 6-14 ; Clear STATUS register (Bank0 Bank1 ; ; Bank0 ; ; Set RP0 and RP1 in STATUS register, other ; bits unchanged (Bank3 Bank2 ; ; Bank0 1997 Microchip Technology Inc. Example 6-4 ...

Page 109

... INCF FSR BTFSS STATUS, C GOTO Bank3_LP : 1997 Microchip Technology Inc. ; Clear STATUS register (Bank0) ; 1st address (in bank) of GPR area ; Move it to Indirect address register ; Clear GPR at address pointed to by FSR ; Next GPR (RAM) address ; End of current bank ? (FSR = 80h NO, clear next location ...

Page 110

... If the device you are using does not use all 4 data memory banks, some of the code may be removed. DS31006A-page 6-16 HIGH (SUB_1) ; Select Program Memory Page of PCLATH ; Routine. SUB_1 ; Call the desired routine ; Start of routine ; Return from routine 1997 Microchip Technology Inc. ...

Page 111

... Mid-range MCU family (that is they may be writ- ten for the Base-Line, or High-End families), but the concepts are pertinent, and could be used (with modification and possible limitations). The current application notes related to memory are: Title Implementing a Table Read 1997 Microchip Technology Inc. 6 Application Note # AN556 DS31006A-page 6-17 ...

Page 112

... PICmicro MID-RANGE MCU FAMILY 6.7 Revision History Revision A This is the initial released revision of the Memory Organization description. DS31006A-page 6-18 1997 Microchip Technology Inc. ...

Page 113

... Write Verify.....................................................................................................................7-6 7.8 Protection Against Spurious Writes ...............................................................................7-7 7.9 Data EEPROM Operation During Code Protected Configuration ..................................7-7 7.10 Initialization ....................................................................................................................7-7 7.11 Design Tips ....................................................................................................................7-8 7.12 Related Application Notes..............................................................................................7-9 7.13 Revision History ...........................................................................................................7-10 1997 Microchip Technology Inc. 7 DS31007A page 7-1 ...

Page 114

... When the device is code protected, the CPU may continue to read and write the data EEPROM memory. The device programmer can no longer access this memory. DS31007A-page 7-2 Table 7-1 shows some of the possible common Address Range 0h - 3Fh 0h - 7Fh 0h - FFh 1997 Microchip Technology Inc. range). DD ...

Page 115

... The RD bit can only be set (not cleared) in software Does not initiate an EEPROM read Legend R = Readable bit U = Unimplemented bit, read as ‘0’ Note 1: Future devices will have this bit in the PIR register. 1997 Microchip Technology Inc. Section 7. Data EEPROM U-0 R/W-1 R/W-1 R/W-x (1) — ...

Page 116

... The data and address will be unchanged in the EEDATA and EEADR registers. Interrupt flag bit EEIF is set when write is complete. It must be cleared in software. EECON2 is not a physical register. Reading EECON2 will read all '0's. The EECON2 register is used exclusively in the Data EEPROM write sequence. DS31007A-page 7-4 1997 Microchip Technology Inc. ...

Page 117

... At the completion of the write cycle, the WR bit is cleared in hardware and the EE Write Complete Interrupt Flag bit (EEIF) is set. The user can either enable this interrupt or poll this bit. EEIF must be cleared by software. 1997 Microchip Technology Inc. Section 7. Data EEPROM ; Bank0 ; Any location in Data EEPROM memory space ...

Page 118

... This STATUS, RP0 ; Bank0 ; Any code can go here ; EEDATA Must be in Bank0 STATUS, RP0 ; Bank1 EECON1 YES, Read the value written STATUS, RP0 ; Bank0 ; ; Is difference 0? WRITE_ERR ; NO, Write error ; YES, Good write ; Continue program 1997 Microchip Technology Inc. ...

Page 119

... Then depending on this mode, the device would do some diagnostic func- tion. The state for the I/O pins would need to be something that would not be possible without the injected levels to force this diagnostic mode. 1997 Microchip Technology Inc. Section 7. Data EEPROM Example 7-1 ...

Page 120

... PICmicro MCU to ensure that no data EEPROM writes occur when the device is out of the valid operating range. DS31007A-page 7-8 Example 7-2. If you are using this code segment ensure that all interrupts 1997 Microchip Technology Inc. ...

Page 121

... EEPROM Endurance Tutorial How to get 10 Million Cycles out of your Microchip Serial EEPROM Basic Serial EEPROM Operation Everything a System Engineer needs to know about Serial EEPROM Endurance Using the Microchip Endurance Predictive Software 1997 Microchip Technology Inc. Section 7. Data EEPROM Application Note # AN601 AN602 ...

Page 122

... PICmicro MID-RANGE MCU FAMILY 7.13 Revision History Revision A This is the initial released revision of the Data EEPROM description. DS31007A-page 7-10 1997 Microchip Technology Inc. ...

Page 123

... Control Registers ...........................................................................................................8-5 8.3 Interrupt Latency ..........................................................................................................8-10 8.4 INT and External Interrupts..........................................................................................8-10 8.5 Context Saving During Interrupts .................................................................................8-11 8.6 Initialization ..................................................................................................................8-14 8.7 Design Tips ..................................................................................................................8-16 8.8 Related Application Notes............................................................................................8-17 8.9 Revision History ...........................................................................................................8-18 1997 Microchip Technology Inc. 8 DS31008A page 8-1 ...

Page 124

... PIR3 and PIE3. The Interrupt Control Register, INTCON, records individual flag bits for core interrupt requests. It also has various individual enable bits and the global interrupt enable bit. DS31008A-page 8-2 1997 Microchip Technology Inc. ...

Page 125

... GIE bit. The inter- rupts which were ignored are still pending to be serviced when the GIE bit is set again. 1997 Microchip Technology Inc. Section 8. Interrupts RETFIE , exits the interrupt routine as well as sets the GIE ...

Page 126

... See specific device data sheet. 2: Some of the original Mid-Range devices had only one peripheral module. These devices do not have the PEIE bit, and have the mod- ule enable bit in the INTCON register. Wake-up (If in SLEEP mode) Interrupt to CPU Clear GIE bit 1997 Microchip Technology Inc. ...

Page 127

... Note 1: In some devices, the RBIE bit may also be known as GPIE and the RBIF bit may be know as GPIF. Note 2: Some devices may not have this feature. For those devices this bit is reserved. Note 3: In devices with only one peripheral interrupt, this bit may be EEIE or ADIE. 1997 Microchip Technology Inc. Section 8. Interrupts R/W-0 R/W-0 ...

Page 128

... Bit location inconsistencies will not be a problem if you use the supplied Microchip Include files for the symbolic use of these bits. This will allow the Assem- bler/Compiler to automatically take care of the placement of these bits by specifying the correct register and bit name. DS31008A-page 8-6 1997 Microchip Technology Inc. ...

Page 129

... Disables the Comparator interrupt Legend R = Readable bit U = Unimplemented bit, read as ‘0’ Note 1: The bit position of the enable bits is device dependent. Please refer to the device data sheet for bit placement. 1997 Microchip Technology Inc. Section 8. Interrupts R/W-0 (Note Writable bit - n = Value at POR reset ...

Page 130

... The USART transmit buffer, TXREG, is empty (cleared when TXREG is written The USART transmit buffer is full bit ADIF: A/D Converter Interrupt Flag bit A/D conversion completed (must be cleared in software The A/D conversion is not complete DS31008A-page 8-8 PIR Register R/W-0 (Note 1) bit 0 1997 Microchip Technology Inc. ...

Page 131

... Comparator input has not changed Legend R = Readable bit U = Unimplemented bit, read as ‘0’ Note 1: The bit position of the flag bits is device dependent. Please refer to the device data sheet for bit placement. 1997 Microchip Technology Inc. Section 8. Interrupts W = Writable bit - n = Value at POR reset 8 DS31008A-page 8-9 ...

Page 132

... SLEEP and for timing of wake- Interrupt Latency 2 PC+1 PC+1 Inst (PC+1) — Inst (PC) Dummy Cycle Dummy Cycle = instruction cycle time 0004h 0005h Inst (0004h) Inst (0005h) Inst (0004h) 1997 Microchip Technology Inc. ...

Page 133

... STATUS_TEMP : : (Interrupt Service Routine (ISR SWAPF STATUS_TEMP,W MOVWF STATUS SWAPF W_TEMP,F SWAPF W_TEMP,W 1997 Microchip Technology Inc. Section 8. Interrupts 8-1: ; Copy Temporary Register ; regardless of current bank ; Swap STATUS nibbles and place ; into W register ; Save STATUS to a Temporary register ; in Bank0 ; Swap original STATUS register value ...

Page 134

... Save STATUS to a Temporary register ; in Bank0 STATUS_TEMP,W ; Swap original STATUS register value ; into W (restores original bank) STATUS ; Restore STATUS register from ; W register W_TEMP,F ; Swap W_Temp nibbles and return ; value to W_Temp W_TEMP,W ; Swap W_Temp restore original ; W value without affecting STATUS 1997 Microchip Technology Inc. ...

Page 135

... W_TEMP, F SWAPF W_TEMP, W BSF STATUS, RP0 RETFIE Restore_WREG SWAPF W_TEMP, F SWAPF W_TEMP, W RETFIE 1997 Microchip Technology Inc. Section 8. Interrupts 8- Bank 0? ; YES, ; NO, Force to Bank 0 ; Store W register ; Swap STATUS register and ; store in STATUS_TEMP ; Set the bit that corresponds to RP0 ; Push completed ; Store W register ...

Page 136

... Swap original STATUS register value ; into W (restores original bank) STATUS ; Restore STATUS register from ; W register W_TEMP,F ; Swap W_Temp nibbles and return ; value to W_Temp W_TEMP,W ; Swap W_Temp restore original ; W value without affecting STATUS ; End this Macro Example 8-6 shows this structure. 1997 Microchip Technology Inc. ...

Page 137

... LCD_INT : BCF PIR1, LCDIF GOTO END_ISR PORTB_INT : END_ISR POP_MACRO RETFIE 1997 Microchip Technology Inc. Section 8. Interrupts ; List Directive, <P16C77.INC> ; Microchip Device Header File <MY_STD.MAC> ; Include my standard macros <APP.MAC> ; File which includes macros specific ; to this application _XT_OSC & _PWRTE_ON & _BODEN_OFF & _CP_OFF & _WDT_ON ...

Page 138

... If interrupts are being used, ensure that the interrupt flag is cleared after servicing that interrupt (but before executing the RETFIE instruction). If the interrupt flag remains set when the RETFIE instruction is executed, program execution immediately returns to the interrupt vector, since there is an outstanding enabled interrupt. DS31008A-page 8-16 1997 Microchip Technology Inc. ...

Page 139

... Base-Line, or High-End families), but the concepts are pertinent, and could be used (with modification and possible limitations). The current application notes related to this section are: Title Using the PortB Interrupt On Change as an External Interrupt 1997 Microchip Technology Inc. Section 8. Interrupts Application Note # DS31008A-page 8-17 AN566 ...

Page 140

... PICmicro MID-RANGE MCU FAMILY 8.9 Revision History Revision A This is the initial released revision of the interrupt description. DS31008A-page 8-18 1997 Microchip Technology Inc. ...

Page 141

... PORTG and the TRISG Register .................................................................................9-12 9.9 GPIO and the TRISGP Register ..................................................................................9-13 9.10 I/O Programming Considerations.................................................................................9-14 9.11 Initialization ..................................................................................................................9-16 9.12 Design Tips ..................................................................................................................9-17 9.13 Related Application Notes............................................................................................9-19 9.14 Revision History ...........................................................................................................9-20 1997 Microchip Technology Inc. 9 DS31009A page 9-1 ...

Page 142

... Figure 9-1: Typical I/O Port Data bus WR PORT WR TRIS RD PORT Note: I/O pin has protection diodes to V DS31009A-page 9 Data Latch TRIS Latch RD TRIS and I/O pin TTL or Schmitt Trigger 1997 Microchip Technology Inc. ...

Page 143

... PORTE is configured for digital I/O. PORTD will over- ride the values in the TRISD register. In this mode the PORTD and PORTE input buffers are TTL. The control bits for the PSP operation are located in TRISE. 1997 Microchip Technology Inc. Section 9. I/O Ports input. The operation of each ...

Page 144

... DS31009A-page 9-4 ; Bank0 ; Initialize PORTA by clearing output ; data latches ; Select Bank1 ; Value used to initialize data direction ; PORTA<3:0> = inputs PORTA<5:4> = outputs ; TRISA<7:6> always read as ' Data Latch TRIS Latch RD TRIS and I/O pin Analog input mode TTL or ST input buffer 1997 Microchip Technology Inc. ...

Page 145

... Figure 9-3: Block Diagram of RA4 Pin Data Bus WR PORT WR TRIS RD PORT To Peripheral Module Note: I/O pin has protection diodes to V 1997 Microchip Technology Inc. Section 9. I/O Ports Data Latch TRIS Latch RD TRIS Q EN only. SS RA4 pin Schmitt Trigger input buffer D 9 DS31009A-page 9-5 ...

Page 146

... Q WR Port CK TRIS Latch TRIS CK RD TRIS RD Port To Peripheral Module Schmitt Trigger Buffer and enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION<7>). V DD weak P pull-up I/O (1) pin TTL Input Buffer Port . SS 1997 Microchip Technology Inc. ...

Page 147

... Figure 9-5: Block Diagram of RB7:RB4 Pins RB7:RB6 in serial programming mode Note 1: I/O pins have diode protection enable weak pull-ups, set the appropriate TRIS bit( sleep mode the device state. 1997 Microchip Technology Inc. Section 9. I/O Ports (2) RBPU Data Latch Data bus ...

Page 148

... I/O pins have diode protection to V DS31009A-page 9-8 ; Bank0 ; Initialize PORTC by clearing output ; data latches ; Select Bank1 ; Value used to initialize data direction ; PORTC<3:0> = inputs, PORTC<5:4> = outputs ; PORTC<7:6> = inputs Data Latch TRIS Latch Q and I/O pin Schmitt Trigger PORT 1997 Microchip Technology Inc. ...

Page 149

... TRISD Figure 9-7: Typical PORTD Block Diagram (in I/O Port Mode) Data Bus WR PORT WR TRIS RD PORT Note: I/O pins have protection diodes to V 1997 Microchip Technology Inc. Section 9. I/O Ports ; Bank0 ; Initialize PORTD by clearing output ; data latches ; Select Bank1 ; Value used to initialize data direction ...

Page 150

... Parallel Slave Port control and status bits. DS31009A-page 9-10 ; Bank0 ; Initialize PORTE by clearing output ; data latches ; Select Bank1 ; Value used to initialize data direction ; PORTE<1:0> = inputs, PORTE<7:2> = outputs Data Latch TRIS Latch RD TRIS Q and I/O pin Schmitt Trigger input buffer D EN 1997 Microchip Technology Inc. ...

Page 151

... LCDSE, SE12 Figure 9-9: PORTF LCD Block Diagram LCD Segment Data LCD Segment Output Enable LCDSE<n> Data Bus RD PORT RD TRIS Note: I/O pins have protection diodes to V 1997 Microchip Technology Inc. Section 9. I/O Ports ; Select Bank2 ; ; Make all PORTF ; digital inputs ...

Page 152

... Figure 9-10: PORTG LCD Block Diagram LCD Segment Data LCD Segment Output Enable LCDSE<n> Data Bus RD PORT RD TRIS DS31009A-page 9-12 ; Select Bank2 ; ; Make all PORTG ; and PORTE<7> digital inputs 1997 Microchip Technology Inc. Digital Input/ LCD Output pin Schmitt Trigger input buffer ...

Page 153

... Interrupt on change is enabled by setting INTCON<3>. If the device configuration bits select one of the external oscillator modes, the GP4 and GP5 pin’s GPIO functions are overridden and these pins are used for the oscillator. 1997 Microchip Technology Inc. Section 9. I/O Ports ; Bank0 ...

Page 154

... The resulting high output currents may damage the chip. DS31009A-page 9-14 PORTB<3:0> Outputs PORT latch PORT pins ---------- --------- ; 01pp pppp 11pp pppp ; 10pp pppp 11pp pppp ; ; 10pp pppp 11pp pppp ; 10pp pppp 10pp pppp 1997 Microchip Technology Inc. ...

Page 155

... NOP instructions is dependent on the effective capacitance C and the frequency of the device. Figure 9-13: I/O Connection Issues PIC16CXXX I/O (1) C PORTx, PINy Note: This is not a capacitor to ground, but the effective capac- itive loading on the trace. 1997 Microchip Technology Inc. Section 9. I/O Ports ...

Page 156

... It is recommended that when initializing the port, the data latch (PORT register) should be initialized first, and then the data direction (TRIS register). This will elim- inate a possible pin glitch, since the PORT data latch values power random state. DS31009A-page 9-16 1997 Microchip Technology Inc. ...

Page 157

... trademark of Philips Corporation. 1997 Microchip Technology Inc. Section 9. I/O Ports 2 C bus is only driven low, and the pin is tristated for a one. DS31009A-page 9-17 ...

Page 158

... A pin configured as analog is expected to have values that may be nei- ther high nor low to a digital pin, or floating. Floating inputs on digital pins are a no-no, and can lead to high current draw in the input buffer, so the input buffer is disabled. DS31009A-page 9-18 1997 Microchip Technology Inc. ...

Page 159

... Communicating with the I Interfacing 93CX6 Serial EEPROMs to the PIC16C5X Microcontrollers Logic Powered Serial EEPROMs Interfacing 24LCXXB Serial EEPROMs to the PIC16C54 Using the 24XX65 and 24XX32 with Stand-alone PIC16C54 Code 1997 Microchip Technology Inc. Section 9. I/O Ports 2 C Bus using the PIC16C5X Application Note # ...

Page 160

... PICmicro MID-RANGE MCU FAMILY 9.14 Revision History Revision A This is the initial released revision of the I/O Ports description. DS31009A-page 9-20 1997 Microchip Technology Inc. ...

Page 161

... Control Register ...........................................................................................................10-3 10.3 Operation .....................................................................................................................10-4 10.4 Operation in Sleep Mode .............................................................................................10-5 10.5 Effect of a Reset...........................................................................................................10-5 10.6 PSP Waveforms ...........................................................................................................10-5 10.7 Design Tips ..................................................................................................................10-6 10.8 Related Application Notes............................................................................................10-7 10.9 Revision History ...........................................................................................................10-8 1997 Microchip Technology Inc. 10 DS31010A page 10-1 ...

Page 162

... Figure 10-1: PORTD and PORTE Block Diagram (Parallel Slave Port) Data bus One bit of PORTD Set interrupt flag PSPIF Note: I/O pins have protection diodes to V DS31010A-page 10 Port Port and PSP7:PSP0 TTL TTL Read RD TTL Chip Select CS TTL Write WR 1997 Microchip Technology Inc. ...

Page 163

... TRISE1: RE1 direction control bit 1 = Input 0 = Output bit 0 TRISE0: RE0 direction control bit 1 = Input 0 = Output Legend R = Readable bit U = Unimplemented bit, read as ‘0’ 1997 Microchip Technology Inc. R/W-0 R/W-0 U-0 R/W-1 IBOV PSPMODE — TRISE2 W = Writable bit - n = Value at POR reset ...

Page 164

... Read operation. Reads PORTD register (if chip selected) Write Control Input in parallel slave port mode Not a write operation 0 = Write operation. Writes PORTD register (if chip selected) Chip Select Control Input in parallel slave port mode Device is not selected 0 = Device is selected cycles (see parameter 66). If the IBF 1997 Microchip Technology Inc. ...

Page 165

... Figure 10-2: Parallel Slave Port Write Waveforms PORTD<7:0> IBF OBF PSPIF Note: The IBF flag bit is inhibited from being cleared until after this point. Figure 10-3: Parallel Slave Port Read Waveforms PORTD<7:0> IBF OBF PSPIF 1997 Microchip Technology Inc DS31010A-page 10-5 ...

Page 166

... Migrating from the PIC16C74 to the PIC16C74A, the operation of the PSP seems to have changed. Answer 1: Yes, a design change was made so the PIC16C74A is edge sensitive (while the PIC16C74 was level sensitive). See DS31010A-page 10-6 Appendix C.9 for more information. 1997 Microchip Technology Inc. ...

Page 167

... Base-Line, or High-End families), but the concepts are pertinent, and could be used (with modification and possible limitations). The current application notes related to the Parallel Slave Port are: Title Using the 8-bit Parallel Slave Port 1997 Microchip Technology Inc. Application Note # AN579 10 DS31010A-page 10-7 ...

Page 168

... PICmicro MID-RANGE MCU FAMILY 10.9 Revision History Revision A This is the initial released revision of the Parallel Slave Port description. DS31010A-page 10-8 1997 Microchip Technology Inc. ...

Page 169

... Control Register ...........................................................................................................11-3 11.3 Operation .....................................................................................................................11-4 11.4 TMR0 Interrupt.............................................................................................................11-5 11.5 Using Timer0 with an External Clock ...........................................................................11-6 11.6 TMR0 Prescaler ...........................................................................................................11-7 11.7 Design Tips ................................................................................................................11-10 11.8 Related Application Notes..........................................................................................11-11 11.9 Revision History .........................................................................................................11-12 1997 Microchip Technology Inc. Section 11. Timer0 11 DS31011A page 11-1 ...

Page 170

... The prescaler is shared with Watchdog Timer (refer to DS31011A-page 11-2 PSout 1 Sync with Internal clocks Programmable 0 Prescaler (2 cycle delay) 3 PS2, PS1, PS0 PSA Figure 11-6 Data bus 8 TMR0 PSout Set interrupt flag bit T0IF on overflow for detailed block diagram). 1997 Microchip Technology Inc. ...

Page 171

... U = Unimplemented bit, read as ‘0’ Note 1: Some devices call this bit GPPU. Devices that have the RBPU bit, have the weak pull-ups on PORTB, while devices that have the GPPU have the weak pull-ups on the GPIO Port. 1997 Microchip Technology Inc. Section 11. Timer0 R/W-1 R/W-1 ...

Page 172

... That is, after the PC+4 PC+5 PC+6 MOVF TMR0,W NT0 NT0+1 NT0+2 T0 Read TMR0 Read TMR0 reads NT0 + 1 reads NT0 + 2 PC+4 PC+5 PC+6 MOVF TMR0,W NT0+1 Read TMR0 Read TMR0 reads NT0 reads NT0 + 1 1997 Microchip Technology Inc. ...

Page 173

... GIE bit INSTRUCTION FLOW PC PC Instruction Inst (PC) fetched Instruction Inst (PC-1) executed Note 1: Interrupt flag bit T0IF is sampled here (every Q1). 2: Interrupt latency = 4T where CLKOUT is available only in RC oscillator mode. 1997 Microchip Technology Inc. Section 11. Timer0 Figure 11 00h 01h Inst (PC+1) ...

Page 174

... The arrows indicate the points in time where sampling occurs. DS31011A-page 11-6 These requirements ensure the external clock ). Also, there is a delay in the actual OSC (Figure parameters 40, 41 parameters 40, ( 11-5). Therefore nec- and 42 in the electrical spec- 41 and 42 in the electrical Small pulse misses sampling 1997 Microchip Technology Inc. ...

Page 175

... T0CKI pin X 1 T0SE T0CS Watchdog Timer PSA WDT Enable bit Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>). 1997 Microchip Technology Inc. Section 11. Timer0 11-6). For simplicity, this counter is being referred to as “prescaler” SYNC Cycles PSA 8-bit Prescaler 1MUX PS2:PS0 ...

Page 176

... WDT, do not change prescale value ; ;Clears WDT and prescaler ;Select new prescale value and WDT ; ;Bank0 ; Clear WDT and prescaler STATUS, RP0 ; Bank1 b'xxxx0xxx' ; Select TMR0, new prescale OPTION_REG ; value and clock source STATUS, RP0 ; Bank0 1997 Microchip Technology Inc. ...

Page 177

... The TMR0 interrupt is disabled, do polling on the overflow bit ; T0_OVFL_WAIT BTFSS INTCON, T0IF GOTO T0_OVFL_WAIT ; Timer has overflowed 1997 Microchip Technology Inc. Section 11. Timer0 Example 11-3 shows the initialization for the internal Example 11-4 shows the initialization for the external clock TMR0 ; Clear Timer0 register INTCON ...

Page 178

... However, since two instruction cycles are lost when you write to TMR0 (for internal logic synchronization), you should actually write 158 to the timer. DS31011A-page 11-10 TMR0,W ; read the timer into W STATUS,Z ; see if it was zero, if so, ; break from loop wait ; if not zero yet, keep waiting 3 TMR0,W STATUS,C Wait 1997 Microchip Technology Inc. ...

Page 179

... Base-Line, or High-End families), but the concepts are pertinent, and could be used (with modification and possible limitations). The current application notes related to Timer0 are: Title Frequency Counter Using PIC16C5X A Clock Design using the PIC16C54 for LED Display and Switch Inputs 1997 Microchip Technology Inc. Section 11. Timer0 Application Note # DS31011A-page 11-11 11 ...

Page 180

... PICmicro MID-RANGE MCU FAMILY 11.9 Revision History Revision A This is the initial released revision of the Timer0 Module description. DS31011A-page 11-12 1997 Microchip Technology Inc. ...

Page 181

... Resetting Timer1 Using a CCP Trigger Output ............................................................12-9 12.9 Resetting of Timer1 Register Pair (TMR1H:TMR1L)....................................................12-9 12.10 Timer1 Prescaler..........................................................................................................12-9 12.11 Initialization ................................................................................................................12-10 12.12 Design Tips ................................................................................................................12-12 12.13 Related Application Notes..........................................................................................12-13 12.14 Revision History .........................................................................................................12-14 1997 Microchip Technology Inc. Section 12. Timer1 12 DS31012A page 12-1 ...

Page 182

... This eliminates power drain. DS31012A-page 12-2 (Figure 12-1). CCP Special Trigger TMR1 CLR TMR1L TMR1H TMR1ON on/off T1OSC 1 T1OSCEN F /4 OSC Enable Internal 0 (1) Oscillator Clock TMR1CS Synchronized 0 clock input 1 T1SYNC Synchronize Prescaler det 2 SLEEP input T1CKPS1:T1CKPS0 1997 Microchip Technology Inc. ...

Page 183

... External clock from pin T1OSO/T1CKI (on the rising edge Internal clock (F bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Legend R = Readable bit U = Unimplemented bit, read as ‘0’ 1997 Microchip Technology Inc. Section 12. Timer1 T1CON: Timer1 Control Register R/W-0 R/W-0 T1CKPS0 T1OSCEN T1SYNC /4) ...

Page 184

... Refer to and 47 in the “Electrical Specifications” DS31012A-page 12-4 /4. The synchronize control bit, T1SYNC (T1CON<2>), has no effect since parameters 45, 46, and 47 in the “Electrical Specifications” section. section. parameters 40, 42, 45, 46, 1997 Microchip Technology Inc. ...

Page 185

... Example 12-1 register. Example 12-1: TMR1 04FFh 0500h 0501h 0502h 1997 Microchip Technology Inc. Section 12. Timer1 Mode”). Since the counter can operate in parameters 45, 46, and 47. shows why this may not be a straight forward read of the 16-bit Reading 16-bit Register Issues Sequence 1 ...

Page 186

... Continue with your code Writing a 16-bit Free Running Timer TMR1L ; Clear Low byte, Ensures no ; rollover into TMR1H HI_BYTE ; Value to load into TMR1H TMR1H Write High byte LO_BYTE ; Value to load into TMR1L TMR1H Write Low byte ; Continue with your code 1997 Microchip Technology Inc. ...

Page 187

... Note 1: Higher capacitance increases the stability of oscillator but also increases the start-up time. 2: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 1997 Microchip Technology Inc. Section 12. Timer1 Freq C1 32 kHz ...

Page 188

... When Timer1 overflows the interrupt could wake-up the device so that the appropriate registers could be updated. Figure 12-2: Timer1 Application power-down detect 32 kHz DS31012A-page 12-8 8 OSC1 PIC16CXXX Backup Battery 4 TMR1 T1OSI 4 T1OSO V SS current sink Keypad 1997 Microchip Technology Inc. ...

Page 189

... T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 Legend unknown unchanged unimplemented read as '0'. Shaded cells are not used by the Timer1 module. Note 1: The placement of this bit is device dependent. 2: These bits may also be named GPIE and GPIF. 1997 Microchip Technology Inc. Section 12. Timer1 Bit 3 Bit 2 Bit 1 ...

Page 190

... Clear Timer1 High byte register ; Clear Timer1 Low byte register ; Disable interrupts ; Bank1 ; Disable peripheral interrupts ; Bank0 ; Clear peripheral interrupts Flags ; External Clock source with 1:8 prescaler ; Clock source is synchronized to device ; Timer1 is stopped and T1 osc is disabled Example 12-6 shows the 1997 Microchip Technology Inc. ...

Page 191

... BTFSS PIR1, TMR1IF GOTO T1_OVFL_WAIT ; ; Timer has overflowed ; BCF PIR1, TMR1IF 1997 Microchip Technology Inc. Section 12. Timer1 ; Stop Timer1, Internal Clock Source oscillator disabled, prescaler = 1:1 ; Clear Timer1 High byte register ; Clear Timer1 Low byte register ; Disable interrupts ; Bank1 ; Disable peripheral interrupts ...

Page 192

... TMR1H register. Normally you write to the TMR1H register if you want the Timer1 overflow interrupt to be sooner then the full 16-bit time-out. 2. You should ensure the your layout uses good PCB layout techniques so that noise does not couple onto the Timer1 oscillator lines. DS31012A-page 12-12 1997 Microchip Technology Inc. ...

Page 193

... The current application notes related to Timer1 are: Title Using Timer1 in Asynchronous Clock Mode Low Power Real Time Clock Yet another Clock using the PIC16C92X 1997 Microchip Technology Inc. Section 12. Timer1 Application Note # DS31012A-page 12-13 AN580 ...

Page 194

... PICmicro MID-RANGE MCU FAMILY 12.14 Revision History Revision A This is the initial released revision of the Timer1 module description. DS31012A-page 12-14 1997 Microchip Technology Inc. ...

Page 195

... TMR2 Match Output.....................................................................................................13-4 13.6 Clearing the Timer2 Prescaler and Postscaler.............................................................13-4 13.7 Sleep Operation ...........................................................................................................13-4 13.8 Initialization ..................................................................................................................13-5 13.9 Design Tips ..................................................................................................................13-6 13.10 Related Application Notes............................................................................................13-7 13.11 Revision History ...........................................................................................................13-8 1997 Microchip Technology Inc. Section 13. Timer2 13 DS31013A page 13-1 ...

Page 196

... F /4 OSC Note: TMR2 register output can be software selected by the SSP Module as a baud clock. DS31013A-page 13-2 Prescaler Reset TMR2 reg 1:1, 1:4, 1:16 2 Comparator EQ T2CKPS1:T2CKPS0 PR2 reg Sets flag TMR2 bit TMR2IF (1) output Postscaler 1:16 1 TOUTPS3:TOUTPS0 1997 Microchip Technology Inc. ...

Page 197

... Timer2 Timer2 is off bit 1:0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 Legend R = Readable bit U = Unimplemented bit, read as ‘0’ 1997 Microchip Technology Inc. Section 13. Timer2 R/W-0 R/W-0 R/W-0 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON W = Writable bit - n = Value at POR reset ...

Page 198

... Bit 1 INTE RBIE T0IF INTF (1) TMR2IF (1) TMR2IE /4). A prescale option OSC Value on: Value on Bit 0 POR, all other BOR, PER resets RBIF 0000 000x 0000 000u 0000 0000 0000 0000 -000 0000 -000 0000 1111 1111 1111 1111 1997 Microchip Technology Inc. ...

Page 199

... The Timer2 interrupt is disabled, do polling on the overflow bit ; T2_OVFL_WAIT BTFSS PIR1, TMR2IF GOTO T2_OVFL_WAIT ; ; Timer has overflowed ; BCF PIR1, TMR2IF 1997 Microchip Technology Inc. Section 13. Timer2 Timer2 Initialization ; Stop Timer2, Prescaler = 1:1, ; Postscaler = 1:1 ; Clear Timer2 register ; Disable interrupts ; Bank1 ; Disable peripheral interrupts ; Bank0 ; Clear peripheral interrupts Flags ...

Page 200

... PICmicro MID-RANGE MCU FAMILY 13.9 Design Tips No related Design Tips at this time. DS31013A-page 13-6 1997 Microchip Technology Inc. ...

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