PIC16F818-I/P Microchip Technology, PIC16F818-I/P Datasheet - Page 99

• Manufacturer Part Number: PIC16F818-I/P
• Description: IC MCU FLASH 1KX14 18-DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F818-I/P

• Program Memory Type: FLASH
• Program Memory Size: 1.75KB (1K x 14)
• Package / Case: 18-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: I2C/SPI/SSP
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ACICE0202 - ADAPTER MPLABICE 18P 300 MILAC164010 - MODULE SKT PROMATEII DIP/SOIC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.2.4
1997 Microchip Technology Inc.
Program Counter (PC)
The program counter (PC) specifies the address of the instruction to fetch for execution. The PC
is 13-bits wide. The low byte is called the PCL register. This register is readable and writable. The
high byte is called the PCH register. This register contains the PC<12:8> bits and is not directly
readable or writable. All updates to the PCH register go through the PCLATH register.
Figure 6-2
loaded on a write to PCL (PCLATH<4:0>
a GOTO instruction (PCLATH<4:3>
CALL instruction (PCLATH<4:3>
Situation 4 shows how the PC is loaded during one of the return instructions where the PC
loaded (POPed) from the Top of Stack.
Figure 6-2: Loading of PC In Different Situations
Situation 1 - Instruction with PCL as destination
Situation 2 - GOTO Instruction
Situation 3 - CALL Instruction
Situation 4 - RETURN, RETFIE, or RETLW Instruction
Section 6. Memory Organization
PC
PC
PC
PC
shows the four situations for the loading of the PC. Situation 1 shows how the PC is
Note: PCLATH is never updated with the contents of PCH.
12
12 11 10
12 11 10
12 11 10
2
2
5
PCH
PCLATH<4:3>
PCH
PCLATH<4:3>
PCH
PCH
PCLATH
PCLATH
PCLATH
PCLATH<4:0>
8
8
8
PCLATH
8
7
7
7
7
PCL
PCL
PCL
PCL
PCH), with the PC loaded (PUSHed) onto the Top of Stack.
PCH). Situation 3 shows how the PC is loaded during a
11
11
11
PCH). Situation 2 shows how the PC is loaded during
8
ALU result
0
0
0
0
13
13
Opcode <10:0>
Opcode <10:0>
Opcode <10:0>
STACK (13-bits x 8)
STACK (13-bits x 8)
STACK (13-bits x 8)
STACK (13-bits x 8)
Top of STACK
Top of STACK
Top of STACK
Top of STACK
DS31006A-page 6-5
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