PIC16F818-I/P Microchip Technology, PIC16F818-I/P Datasheet - Page 74

• Manufacturer Part Number: PIC16F818-I/P
• Description: IC MCU FLASH 1KX14 18-DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F818-I/P

• Program Memory Type: FLASH
• Program Memory Size: 1.75KB (1K x 14)
• Package / Case: 18-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: I2C/SPI/SSP
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ACICE0202 - ADAPTER MPLABICE 18P 300 MILAC164010 - MODULE SKT PROMATEII DIP/SOIC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16F818/819
REGISTER 10-1:
DS39598E-page 72
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SSPSTAT: SYNCHRONOUS SERIAL PORT STATUS REGISTER (ADDRESS 94h)
bit 7
SMP: SPI Data Input Sample Phase bit
SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time (Microwire)
SPI Slave mode:
This bit must be cleared when SPI is used in Slave mode.
I
This bit must be maintained clear.
CKE: SPI Clock Edge Select bit
1 = Transmit occurs on transition from active to Idle clock state
0 = Transmit occurs on transition from Idle to active clock state
I
This bit must be maintained clear.
D/A: Data/Address bit (I
In I
1 = Indicates that the last byte received was data
0 = Indicates that the last byte received was address
P: Stop bit
1 = Indicates that a Stop bit has been detected last
0
S: Start bit
1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset)
0
R/W: Read/Write Information bit (I
Holds the R/W bit information following the last address match and is only valid from address
match to the next Start bit, Stop bit or ACK bit.
1 = Read
0
UA: Update Address bit (10-bit I
1 = Indicates that the user needs to update the address in the SSPADD register
0
BF: Buffer Full Status bit
Receive (SPI and I
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit (In I
1 = Transmit in progress, SSPBUF is full (8 bits)
0 = Transmit complete, SSPBUF is empty
2
2
Legend:
R = Readable bit
-n = Value at POR
C mode:
C mode:
= Stop bit was not detected last
= Start bit was not detected last
= Write
= Address does not need to be updated
Note:
Note 1: This bit is cleared when the SSP module is disabled (i.e., the SSPEN bit is cleared).
R/W-0
SMP
2
C Slave mode:
(1)
(1)
Polarity of clock state is set by the CKP bit (SSPCON<4>).
(I
2
(I
C mode only):
R/W-0
2
2
CKE
C mode only)
C mode only)
2
C modes):
2
C mode only)
R-0
D/A
W = Writable bit
‘1’ = Bit is set
2
C mode only)
2
C mode only)
R-0
P
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R-0
S
R/W
R-0
 2004 Microchip Technology Inc.
x = Bit is unknown
R-0
UA
R-0
BF
bit 0