ATMEGA16U4-MU Atmel, ATMEGA16U4-MU Datasheet - Page 177
ATMEGA16U4-MU
Manufacturer Part Number
ATMEGA16U4-MU
Description
MCU AVR 16K FLASH 16MHZ 44-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA16U4-MU.pdf
(433 pages)
Specifications of ATMEGA16U4-MU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
26
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-VQFN
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ATMEGA16U4-16MU
ATMEGA16U4-16MU
ATMEGA16U4-16MU
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17. Serial Peripheral Interface – SPI
7766F–AVR–11/10
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the
ATmega16U4/ATmega32U4 and peripheral devices or between several AVR devices. The
ATmega16U4/ATmega32U4 SPI includes the following features:
•
•
•
•
•
•
•
•
USART can also be used in Master SPI mode, see “USART in SPI Mode” on page 214.
The Power Reduction SPI bit, PRSPI, in
page 50 must be written to zero to enable SPI module.
Figure 17-1. SPI Block Diagram
Note:
The interconnection between Master and Slave CPUs with SPI is shown in
tem consists of two shift Registers, and a Master clock generator. The SPI Master initiates the
Full-duplex, Three-wire Synchronous Data Transfer
Master or Slave Operation
LSB First or MSB First Data Transfer
Seven Programmable Bit Rates
End of Transmission Interrupt Flag
Write Collision Flag Protection
Wake-up from Idle Mode
Double Speed (CK/2) Master SPI Mode
1. Refer to
/2/4/8/16/32/64/128
pin placement.
DIVIDER
“Pinout ATmega16U4/ATmega32U4” on page
(1)
“Power Reduction Register 0 - PRR0” on page 46
3, and
ATmega16/32U4
Table 10-3 on page 72
Figure
17-2. The sys-
for SPI
177
on
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