ATTINY44-15MZ Atmel, ATTINY44-15MZ Datasheet - Page 58
![MCU AVR 4K FLASH 15MHZ 20-QFN](/photos/12/32/123214/20-qfn-pc_sml.jpg)
ATTINY44-15MZ
Manufacturer Part Number
ATTINY44-15MZ
Description
MCU AVR 4K FLASH 15MHZ 20-QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY44-15MZ.pdf
(225 pages)
Specifications of ATTINY44-15MZ
Package / Case
20-QFN Exposed Pad
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Speed
16MHz
Number Of I /o
12
Eeprom Size
256 x 8
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
256 x 8
Program Memory Size
4KB (4K x 8)
Data Converters
A/D 8x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Connectivity
USI
Core Size
8-Bit
Processor Series
ATTINY4x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SPI, UART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY44-15MZ
Manufacturer:
ATMEL
Quantity:
1 000
Part Number:
ATTINY44-15MZ
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- Current page: 58 of 225
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12.2.2
12.2.3
12.2.4
58
Atmel ATtiny24/44/84 [Preliminary]
Toggling the Pin
Switching Between Input and Output
Reading the Pin Value
If PORTxn is written logical one when the pin is configured as an output pin, the port pin is
driven high (one). If PORTxn is written logical zero when the pin is configured as an output pin,
the port pin is driven low (zero).
Writing a logical one to PINxn toggles the value of PORTxn, independent on the value of
DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port.
When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn,
PORTxn} = 0b11), an intermediate state with either pull-up enabled ({DDxn, PORTxn} = 0b01)
or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully
acceptable, as a high-impedance environment will not notice the difference between a strong
high driver and a pull-up. If this is not the case, the PUD bit in the MCUCR register can be set
to disable all pull-ups in all ports.
Switching between input with pull-up and output low generates the same problem. The user
must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn,
PORTxn} = 0b10) as an intermediate step.
Table 12-1 on page 58
Table 12-1.
Independent of the setting of Data Direction bit DDxn, the port pin can be read through the
PINxn Register bit. As shown in
ceding latch constitute a synchronizer. This is needed to avoid metastability if the physical pin
changes value near the edge of the internal clock, but it also introduces a delay.
on page 59
pin value. The maximum and minimum propagation delays are denoted t
respectively.
DDxn
0
0
0
1
1
PORTxn
shows a timing diagram of the synchronization when reading an externally applied
0
1
1
0
1
Port Pin Configurations
(in MCUCR)
summarizes the control signals for the pin value.
PUD
X
0
1
X
X
Figure 12-2 on page
Output
Output
Input
Input
Input
I/O
Pull-up
Yes
No
No
No
No
57, the PINxn Register bit and the pre-
Comment
Tri-state (Hi-Z)
Pxn will source current if ext. pulled low.
Tri-state (Hi-Z)
Output Low (Sink)
Output High (Source)
pd,max
7701E–AVR–02/11
Figure 12-3
and t
pd,min
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