ATMEGA32U4-MUR Atmel, ATMEGA32U4-MUR Datasheet - Page 156

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ATMEGA32U4-MUR

Manufacturer Part Number
ATMEGA32U4-MUR
Description
MCU AVR 16K FLASH 16MHZ 44VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet

Specifications of ATMEGA32U4-MUR

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
26
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-VQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA32U4-MUR
Manufacturer:
UCC
Quantity:
1 001
15.9
7766F–AVR–11/10
Timer/Counter Timing Diagrams
Table 15-5.
The Timer/Counter is a synchronous design and the timer clock (clk
clock enable signal in the following figures. The figures include information on when Interrupt
Flags are set.
Figure 15-16
sequence close to the MAX value in all modes other than Phase and Frequency Correct PWM
Mode.
other than Phase and Frequency Correct PWM Mode.
OCF4A, OCF4B and OCF4D in all modes, and
Phase and Frequency Correct PWM Mode.
Figure 15-16. Timer/Counter Timing Diagram, no Prescaling
Figure 15-17. Timer/Counter Timing Diagram, with Prescaler (f
TCNTn
(clk
TCNTn
(clk
COM4A1
1
1
COM4D1
0
0
1
1
TOVn
TOVn
clk
clk
clk
clk
PCK
PCK
PCK
Tn
PCK
Tn
/1)
/8)
Figure 15-17
contains timing data for basic Timer/Counter operation. The figure shows the count
Output Compare Pin configurations in PWM6 Mode (Continued)
COM4A0
0
1
COM4D0
0
1
0
1
TOP - 1
TOP - 1
shows the same timing data, but with the prescaler enabled, in all modes
OC4A Pin (PC6)
OC4A •
OC4A •
OC4D Pin (PD6)
Disconnected
OC4A •
OC4A •
OC4A •
TOP
TOP
OC4OE2
OC4OE2
OC4OE4
OC4OE4
OC4OE4
Figure 15-19
BOTTOM
BOTTOM
Figure 15-18
clkT4
ATmega16/32U4
shows the setting of TOV4 in
OC4A Pin (PC7)
OC4A •
OC4A •
OC4D Pin (PD7)
Disconnected
OC4A •
OC4A •
OC4A •
/8)
T4
) is therefore shown as a
shows the setting of
OC4OE3
OC4OE3
OC4OE5
OC4OE5
OC4OE5
BOTTOM + 1
BOTTOM + 1
156

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