ATMEGA32U4-MUR Atmel, ATMEGA32U4-MUR Datasheet - Page 209
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ATMEGA32U4-MUR
Manufacturer Part Number
ATMEGA32U4-MUR
Description
MCU AVR 16K FLASH 16MHZ 44VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA16U4-MU.pdf
(433 pages)
Specifications of ATMEGA32U4-MUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
26
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-VQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA32U4-MUR
Manufacturer:
UCC
Quantity:
1 001
- Current page: 209 of 433
- Download datasheet (9Mb)
18.10.5
18.10.6
18.11 Examples of Baud Rate Setting
7766F–AVR–11/10
USART Control and Status Register n D– UCSRnD
USART Baud Rate Registers – UBRRLn and UBRRHn
• Bits 7:2 – Reserved bits
These bits are reserved and will be read as ‘0’. Do not set these bits.
• Bits 1 – CTSEN: UART CTS Signal Enable
Set this bit by firmware to enable the transmission flow control signal (CTS). Transmission will
be enabled only if CTS input = 0. Clear this bit to disable the transmission flow control signal.
Transmission will occur without hardware condition. Data Direction Register bit must be correctly
clear to enable the pin as an input.
• Bits 0 – RTSEN: UART RTS Signal Enable
Set this bit by firmware to enable the reception flow control signal (RTS). In this case the RTS
line will automatically rise when the FIFO is full. Clear this bit to disable the reception flow control
signal. Data Direction Register bit must be correctly set to enable the pin as an output.
• Bit 15:12 – Reserved Bits
These bits are reserved for future use. For compatibility with future devices, these bit must be
written to zero when UBRRH is written.
• Bit 11:0 – UBRR11:0: USART Baud Rate Register
This is a 12-bit register which contains the USART baud rate. The UBRRH contains the four
most significant bits, and the UBRRL contains the eight least significant bits of the USART baud
rate. Ongoing transmissions by the Transmitter and Receiver will be corrupted if the baud rate is
changed. Writing UBRRL will trigger an immediate update of the baud rate prescaler.
For standard crystal and resonator frequencies, the most commonly used baud rates for asyn-
chronous operation can be generated by using the UBRR settings in
UBRR values which yield an actual baud rate differing less than 0.5% from the target baud rate,
are bold in the table. Higher error ratings are acceptable, but the Receiver will have less noise
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
7
R/W
0
15
UBRR[7:0]
7
R
R/W
0
0
–
–
6
R/W
0
14
6
R
R/W
0
0
–
–
13
5
R
R/W
0
0
R/W
5
0
–
–
12
4
R
R/W
0
0
R/W
4
0
–
–
11
UBRR[11:8]
3
R/W
R/W
0
0
3
R/W
0
–
10
2
R/W
R/W
0
0
2
R/W
0
–
9
1
R/W
R/W
0
0
1
CTSEN
R/W
0
ATmega16/32U4
Table 18-9
8
0
R/W
R/W
0
0
0
RTSEN
R/W
0
UBRRHn
UBRRLn
to
UCSRnD
Table
18-12.
209
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