ATMEGA32U4-MUR Atmel, ATMEGA32U4-MUR Datasheet - Page 365
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ATMEGA32U4-MUR
Manufacturer Part Number
ATMEGA32U4-MUR
Description
MCU AVR 16K FLASH 16MHZ 44VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA16U4-MU.pdf
(433 pages)
Specifications of ATMEGA32U4-MUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
26
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-VQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA32U4-MUR
Manufacturer:
UCC
Quantity:
1 001
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Table 28-16. Serial Programming Instruction Set (Continued)
Note:
28.8.2
28.9
28.9.1
7766F–AVR–11/10
Instruction
Read Extended Fuse Bits
Read Calibration Byte
Poll RDY/BSY
a = address high bits, b = address low bits, c = address extended bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in,
x = don’t care
Programming via the JTAG Interface
Serial Programming Characteristics
Programming Specific JTAG Instructions
For characteristics of the Serial Programming module see “SPI Timing Characteristics” on page
383.
Programming through the JTAG interface requires control of the four JTAG specific pins: TCK,
TMS, TDI, and TDO. Control of the reset and clock pins is not required.
To be able to use the JTAG interface, the JTAGEN Fuse must be programmed. The device is
default shipped with the fuse programmed. In addition, the JTD bit in MCUCSR must be cleared.
Alternatively, if the JTD bit is set, the external reset can be forced low. Then, the JTD bit will be
cleared after two chip clocks, and the JTAG pins are available for programming. This provides a
means of using the JTAG pins as normal port pins in Running mode while still allowing In-Sys-
tem Programming via the JTAG interface. Note that this technique can not be used when using
the JTAG pins for Boundary-scan or On-chip Debug. In these cases the JTAG pins must be ded-
icated for this purpose.
During programming the clock frequency of the TCK Input must be less than the maximum fre-
quency of the chip. The System Clock Prescaler can not be used to divide the TCK Clock Input
into a sufficiently low frequency.
As a definition in this datasheet, the LSB is shifted in and out first of all Shift Registers.
The Instruction Register is 4-bit wide, supporting up to 16 instructions. The JTAG instructions
useful for programming are listed below.
The OPCODE for each instruction is shown behind the instruction name in hex format. The text
describes which Data Register is selected as path between TDI and TDO for each instruction.
The Run-Test/Idle state of the TAP controller is used to generate internal clocks. It can also be
used as an idle state between JTAG sequences. The state machine sequence for changing the
instruction word is shown in
0101 0000
0011 1000
1111 0000
Byte 1
0000 1000
000x xxxx
0000 0000
Byte 2
Instruction Format
Figure
xxxx xxxx
0000 0000
xxxx xxxx
Byte 3
28-12.
oooo oooo
oooo oooo
xxxx xxxo
Byte4
Operation
Read Extended Fuse bits. “0” = pro-
grammed, “1” = unprogrammed. See
Table 28-3 on page 347
Read Calibration Byte
If o = “1”, a programming operation is
still busy. Wait until this bit returns to
“0” before applying another command.
ATmega16/32U4
for details.
365
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