ATMEGA324PA-CUR Atmel, ATMEGA324PA-CUR Datasheet - Page 335
ATMEGA324PA-CUR
Manufacturer Part Number
ATMEGA324PA-CUR
Description
MCU AVR 32KB FLSH 20 MHZ 49VFBGA
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA324PA-AUR.pdf
(468 pages)
Specifications of ATMEGA324PA-CUR
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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27.6
8152G–AVR–11/09
SPI Timing Characteristics
See
Table 27-11. SPI Timing Parameters
Note:
Figure 27-3. SPI Interface Timing Requirements (Master Mode)
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
Figure 27-3 on page 335
(Data Output)
(Data Input)
(CPOL = 0)
(CPOL = 1)
1. In SPI Programming mode the minimum SCK high/low period is:
- 2 t
- 3 t
MISO
MOSI
SS high to tri-state
SCK
SCK
SCK to out high
SCK to SS high
SCK high/low
SS low to SCK
SS
Rise/Fall time
Rise/Fall time
SCK high/low
SS low to out
Description
CLCL
CLCL
SCK period
SCK period
Out to SCK
SCK to out
SCK to out
Setup
Setup
Hold
Hold
for f
for f
CK
CK
< 12 MHz
> 12 MHz
6
4
(1)
MSB
ATmega164PA/324PA/644PA/1284P
5
MSB
and
Figure 27-4 on page 336
Master
Master
Master
Master
Master
Master
Master
Master
Mode
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
7
...
4 • t
2 • t
...
Min
10
t
20
20
ck
ck
ck
for details.
See
50% duty cycle
2
0.5 • t
Table 17-5
Typ
3.6
10
10
15
10
10
15
10
LSB
1
sck
LSB
2
3
Max
1600
8
ns
335
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