ATXMEGA32A4-CUR Atmel, ATXMEGA32A4-CUR Datasheet - Page 123
ATXMEGA32A4-CUR
Manufacturer Part Number
ATXMEGA32A4-CUR
Description
MCU AVR 32+4 FLASH 49VFBGA
Manufacturer
Atmel
Series
AVR® XMEGAr
Specifications of ATXMEGA32A4-CUR
Core Processor
AVR
Core Size
8/16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 3.6 V
Data Converters
A/D 12x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
49-VFBGA
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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12. Interrupts and Programmable Multi-level Interrupt Controller
12.1
12.2
12.3
8077H–AVR–12/09
Features
Overview
Operation
•
•
•
•
Interrupts signal a change of state in peripherals, and this can be used to alter program execu-
tion. Peripherals can have one or more interrupts, and all are individually enabled. When the
interrupt is enabled and the interrupt condition is present this will generate a corresponding inter-
rupt request. All interrupts have a separate interrupt vector address.
The Programmable Multi-level Interrupt Controller (PMIC) controls the handling of interrupt
requests, and prioritizing between the different interrupt levels and interrupt priorities. When an
interrupt request is acknowledged by the PMIC, the program counter is set to point to the inter-
rupt vector, and the interrupt handler can be executed.
All peripherals can select between three different priority levels for their interrupts; low, medium
or high. Medium level interrupts will interrupt low level interrupt handlers. High level interrupts
will interrupt both medium and low level interrupt handlers. Within each level, the interrupt prior-
ity is decided from the interrupt vector address, where the lowest interrupt vector address has
the highest interrupt priority. Low level interrupts have an optional round-robin scheduling
scheme to ensure that all interrupts are serviced within a certain amount of time.
Non-Maskable Interrupts (NMI) are also supported.
Interrupts must be globally enabled for any interrupts to be generated. This is done by setting
the global interrupt enable bit (I-bit) in the CPU Status Register. The I-bit will not be cleared
when an interrupt is acknowledged. Each interrupt level must also be enabled before interrupts
with the corresponding level can be generated.
When an interrupt is enabled and the interrupt condition is present, the PMIC will receive the
interrupt request. Based on the interrupt level and interrupt priority of any ongoing interrupts, the
interrupt is either acknowledged or kept pending until it has priority. When the interrupt request
is acknowledged, the program counter is updated to point to the interrupt vector. The interrupt
vector is normally a jump to the interrupt handler; the software routine that handles the interrupt.
After returning from the interrupt handler, program execution continues from where it was before
the interrupt occurred. One instruction is always executed before any pending interrupt is
served.
The PMIC status register contains state information that ensures that the PMIC returns to the
correct interrupt level when the RETI (interrupt return) instruction is executed at the end of an
interrupt handler. Returning from an interrupt will return the PMIC to the state it had before enter-
ing the interrupt. The Status Register (SREG) is not saved automatically upon an interrupt
Separate interrupt vector for each interrupt
Short, predictable interrupt response time
Programmable Multi-level Interrupt Controller
Interrupt vectors can be moved to the start of the Boot Section.
– 3 programmable interrupt levels
– Selectable priority scheme within low level interrupts (round-robin or fixed)
– Non-Maskable Interrupts (NMI)
XMEGA A
123
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