ATMEGA16-16MQ Atmel, ATMEGA16-16MQ Datasheet - Page 143

• Manufacturer Part Number: ATMEGA16-16MQ
• Description: MCU AVR 16K FLASH 16MHZ 44-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA16-16MQ

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-VQFN Exposed Pad
• Processor Series: ATMEGA16x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• For Use With: ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Data Modes
2466T–AVR–07/10
There are four combinations of SCK phase and polarity with respect to serial data, which are
determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in
67
ensuring sufficient time for data signals to stabilize. This is clearly seen by summarizing
56
Table 59. CPOL and CPHA Functionality
Figure 67. SPI Transfer Format with CPHA = 0
Figure 68. SPI Transfer Format with CPHA = 1
and
and
CPOL = 0, CPHA = 0
CPOL = 0, CPHA = 1
CPOL = 1, CPHA = 0
CPOL = 1, CPHA = 1
Table
Figure
SCK (CPOL = 0)
mode 0
SCK (CPOL = 1)
mode 2
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SCK (CPOL = 0)
mode 1
SCK (CPOL = 1)
mode 3
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SS
SS
MSB first (DORD = 0)
LSB first (DORD = 1)
MSB first (DORD = 0)
LSB first (DORD = 1)
57, as done below:
68. Data bits are shifted out and latched in on opposite edges of the SCK signal,
MSB
LSB
Sample (Falling)
Sample (Rising)
Leading Edge
Setup (Rising)
Setup (Falling)
MSB
LSB
Bit 6
Bit 1
Bit 6
Bit 1
Bit 5
Bit 2
Bit 5
Bit 2
Bit 4
Bit 3
Bit 4
Bit 3
Sample (Falling)
Sample (Rising)
Setup (Falling)
Trailing Edge
Setup (Rising)
Bit 3
Bit 4
Bit 3
Bit 4
Bit 2
Bit 5
Bit 2
Bit 5
ATmega16(L)
Bit 1
Bit 6
Bit 1
Bit 6
SPI Mode
LSB
MSB
0
1
2
3
LSB
MSB
Figure
Table
143