PIC16C55-XTI/SS Microchip Technology, PIC16C55-XTI/SS Datasheet - Page 15

• Manufacturer Part Number: PIC16C55-XTI/SS
• Description: IC MCU OTP 512X12 28SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C55-XTI/SS

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 20
• Program Memory Size: 768B (512 x 12)
• Program Memory Type: OTP
• Ram Size: 24 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 6.25 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SSOP
• For Use With: 309-1026 - ADAPTER 28-SSOP TO 28-DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -

3.1
The clock input (OSC1/CLKIN pin) is internally divided
by four to generate four non-overlapping quadrature
clocks, namely Q1, Q2, Q3 and Q4. Internally, the pro-
gram counter is incremented every Q1 and the instruc-
tion is fetched from program memory and latched into
the instruction register in Q4. It is decoded and exe-
cuted during the following Q1 through Q4. The clocks
and instruction execution flow are shown in Figure 3-2
and Example 3-1.
FIGURE 3-2:
EXAMPLE 3-1:
1. MOVLW H’55’
2. MOVWF PORTB
3. CALL
4. BSF
2002 Microchip Technology Inc.
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is “flushed” from the pipeline, while the new instruction is being fetched and then executed.
OSC2/CLKOUT
Clocking Scheme/Instruction
Cycle
(RC mode)
SUB_1
PORTA, BIT3
OSC1
Q4
PC
Q2
Q3
Q1
CLOCK/INSTRUCTION CYCLE
INSTRUCTION PIPELINE FLOW
Q1
Execute INST (PC-1)
Fetch INST (PC)
Q2
Fetch 1
PC
Q3
Execute 1
Q4
Fetch 2
Preliminary
Q1
Execute INST (PC)
Fetch INST (PC+1)
Execute 2
Q2
Fetch 3
PC+1
3.2
An Instruction Cycle consists of four Q cycles (Q1, Q2,
Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle,
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO),
then two cycles are required to complete the instruction
(Example 3-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the Instruction Register in cycle Q1. This instruc-
tion is then decoded and executed during the Q2, Q3
and Q4 cycles. Data memory is read during Q2 (oper-
and read) and written during Q4 (destination write).
Q3
Execute 3
Q4
Fetch 4
Instruction Flow/Pipelining
Q1
Fetch SUB_1 Execute SUB_1
Execute INST (PC+1)
Fetch INST (PC+2)
Q2
Flush
PC+2
PIC16C5X
Q3
Q4
DS30453D-page 13
Internal
phase
clock