AT91SAM7S321-MU-999 Atmel, AT91SAM7S321-MU-999 Datasheet
AT91SAM7S321-MU-999
Specifications of AT91SAM7S321-MU-999
Related parts for AT91SAM7S321-MU-999
AT91SAM7S321-MU-999 Summary of contents
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... Kbytes (AT91SAM7S128) Organized in 512 Pages of 256 Bytes (Single Plane) – 64 Kbytes (AT91SAM7S64) Organized in 512 Pages of 128 Bytes (Single Plane) – 32 Kbytes (AT91SAM7S321/32) Organized in 256 Pages of 128 Bytes (Single Plane) – 16 Kbytes (AT91SAM7S161/16) Organized in 256 Pages of 64 Bytes (Single Plane) – ...
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... One Two-wire Interface (TWI) – Master Mode Support Only, All Two-wire Atmel EEPROMs and I (AT91SAM7S512/256/128/64/321/32) – Master, Multi-Master and Slave Mode Support, All Two-wire Atmel EEPROMs and I (AT91SAM7S161/16) • One 8-channel 10-bit Analog-to-Digital Converter, Four Channels Multiplexed with Digital I/Os ™ ...
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... Their aggressive price point and high level of integration pushes their scope of use far into the cost-sensitive, high-volume consumer market. 1.1 Configuration Summary of the AT91SAM7S512, AT91SAM7S256, AT91SAM7S128, AT91SAM7S64, AT91SAM7S321, AT91SAM7S32, AT91SAM7S161 and AT91SAM7S16 The AT91SAM7S512, AT91SAM7S256, AT91SAM7S128, AT91SAM7S64, AT91SAM7S321, AT91SAM7S32, AT91SAM7S161 and AT91SAM7S16 differ in memory size, peripheral set and package. ...
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Block Diagram Figure 2-1. AT91SAM7S512/256/128/64/321/161 Block Diagram TDI TDO JTAG TMS SCAN TCK JTAGSEL System Controller TST FIQ IRQ0-IRQ1 PCK0-PCK2 PLLRC PLL XIN OSC XOUT RCOSC VDDCORE BOD POR VDDCORE NRST DRXD DTXD RXD0 TXD0 SCK0 RTS0 CTS0 RXD1 ...
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Figure 2-2. AT91SAM7S32/16 Block Diagram TDI TDO TMS TCK JTAGSEL System Controller TST FIQ IRQ0 PCK0-PCK2 PLLRC PLL XIN OSC XOUT VDDCORE BOD POR VDDCORE NRST DRXD DTXD RXD0 TXD0 SCK0 RTS0 CTS0 NPCS0 NPCS1 NPCS2 NPCS3 MISO MOSI SPCK ...
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Signal Description Table 3-1. Signal Description List Signal Name Function Voltage and ADC Regulator Power Supply VDDIN Input VDDOUT Voltage Regulator Output VDDFLASH Flash Power Supply VDDIO I/O Lines Power Supply VDDCORE Core Power Supply VDDPLL PLL GND Ground ...
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Table 3-1. Signal Description List (Continued) Signal Name Function DDM USB Device Port Data - DDP USB Device Port Data + SCK0 - SCK1 Serial Clock TXD0 - TXD1 Transmit Data RXD0 - RXD1 Receive Data RTS0 - RTS1 Request ...
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Table 3-1. Signal Description List (Continued) Signal Name Function TWD Two-wire Serial Data TWCK Two-wire Serial Clock AD0-AD3 Analog Inputs AD4-AD7 Analog Inputs ADTRG ADC Trigger ADVREF ADC Reference PGMEN0-PGMEN2 Programming Enabling PGMM0-PGMM3 Programming Mode PGMD0-PGMD15 Programming Data PGMRDY Programming ...
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Package and Pinout The AT91SAM7S512/256/128/64/321 are available in a 64-lead LQFP or 64-pad QFN package. The AT91SAM7S161 is available in a 64-Lead LQFP package. The AT91SAM7S32/16 are available in a 48-lead LQFP or 48-pad QFN package. 4.1 64-lead LQFP ...
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LQFP and 64-pad QFN Pinout Table 4-1. AT91SAM7S512/256/128/64/321/161 Pinout 1 ADVREF 17 2 GND 18 3 AD4 19 4 AD5 20 5 AD6 21 6 AD7 22 7 VDDIN 23 8 VDDOUT 24 9 PA17/PGMD5/AD0 25 10 PA18/PGMD6/AD1 ...
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LQFP and 48-pad QFN Package Outlines Figure 4-3 age. A detailed mechanical description is given in the section Mechanical Characteristics of the full datasheet. Figure 4-3. Figure 4-4. 4.4 48-lead LQFP and 48-pad QFN Pinout Table 4-2. AT91SAM7S32/16 ...
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Power Considerations 5.1 Power Supplies The AT91SAM7S Series has six types of power supply pins and integrates a voltage regulator, allowing the device to be supplied with only one voltage. The six power supply pin types are: • VDDIN ...
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Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability and reduce source voltage drop. The input decoupling capacitor should be placed close to the chip. For example, two capacitors can be used in parallel: 100 ...
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I/O Lines Considerations 6.1 JTAG Port Pins TMS, TDI and TCK are schmitt trigger inputs. TMS and TCK are 5-V tolerant, TDI is not. TMS, TDI and TCK do not integrate a pull-up resistor. TDO is an output, driven ...
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I/O line to VDDIO. Care should be taken, in particular at reset, as all the I/O lines default to input with the pull-up resistor enabled at reset. 6.6 I/O Line Drive Levels The PIO lines PA0 to ...
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Processor and Architecture 7.1 ARM7TDMI Processor • RISC processor based on ARMv4T Von Neumann architecture – Runs MHz, providing 0.9 MIPS/MHz • Two instruction sets – ARM – Thumb • Three-stage pipeline architecture – Instruction ...
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Prefetch buffer, buffering and anticipating the 16-bit requests, reducing the required – Key-protected program, erase and lock/unlock sequencer – Single command for erasing, programming and locking operations – Interrupt generation in case of forbidden operation 7.4 Peripheral DMA Controller ...
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Memories 8.1 AT91SAM7S512 • 512 Kbytes of Flash Memory, dual plane – 2 contiguous banks of 1024 pages of 256 bytes – Fast access time, 30 MHz single-cycle access in Worst Case conditions – Page programming time: 6 ms, ...
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... Protection Mode to secure contents of the Flash • 16 Kbytes of Fast SRAM – Single-cycle access at full speed 8.5 AT91SAM7S321/32 • 32 Kbytes of Flash Memory, single plane – 256 pages of 128 bytes – Fast access time, 30 MHz single-cycle access in Worst Case conditions – Page programming time: 6 ms, including page auto-erase – ...
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Figure 8-1. AT91SAM7S512/256/128/64/321/32/161/16 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 256 MBytes 0x0FFF FFFF 0x1000 0000 Undefined 14 x 256 MBytes (Abort) 3,584 MBytes 0xEFFF FFFF 0xF000 0000 Internal Peripherals 256M Bytes 0xFFFF FFFF AT91SAM7S Series Summary 20 ...
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... The AT91SAM7S128 features one bank (single plane) of 128 Kbytes of Flash. • The AT91SAM7S64 features one bank (single plane Kbytes of Flash. • The AT91SAM7S321/32 features one bank (single plane Kbytes of Flash. • The AT91SAM7S161/16 features one bank (single plane Kbytes of Flash. ...
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... The Flash of the AT91SAM7S64 is organized in 512 pages (single plane) of 128 bytes. The 65,536 bytes are organized in 32-bit words. • The Flash of the AT91SAM7S321/32 is organized in 256 pages (single plane) of 128 bytes. The 32,768 bytes are organized in 32-bit words. • The Flash of the AT91SAM7S161/16 is organized in 256 pages (single plane bytes. ...
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Lock Regions 8.8.3.1 AT91SAM7S512 Two Embedded Flash Controllers each manage 16 lock bits to protect 16 regions of the flash against inadvertent flash erasing or programming commands. The AT91SAM7S512 contains 32 lock regions and each lock region contains 64 ...
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... AT91SAM7S321/32 The Embedded Flash Controller manages 8 lock bits to protect 8 regions of the flash against inadvertent flash erasing or programming commands. The AT91SAM7S321/32 contains 8 lock regions and each lock region contains 32 pages of 128 bytes. Each lock region has a size of 4 Kbytes locked-region’s erase or program command occurs, the command is aborted and the LOCKE bit in the MC_FSR register rises and the interrupt line rises if the LOCKE bit has been written the MC_FMR register ...
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Security Bit Feature The AT91SAM7S Series features a security bit, based on a specific NVM Bit. When the security is enabled, any access to the Flash, either through the ICE interface or through the Fast Flash Programming Interface, is ...
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The SAM-BA Boot Assistant is a default Boot Program that provides an easy way to program in situ the on-chip Flash memory. The SAM-BA Boot Assistant supports serial communication through the DBGU or through the USB Device Port. (The AT91SAM7S32/16 ...
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Figure 9-1. System Controller Block Diagram (AT91SAM7S512/256/128/64/321/161) NRST XIN XOUT PLLRC PA0-PA31 6175IS–ATARM–30-Aug-10 AT91SAM7S Series Summary wdt_irq dbgu_irq pmc_irq rstc_irq MCK Debug periph_nreset Unit dbgu_rxd Periodic MCK debug Interval periph_nreset Timer SLCK Real-Time Timer periph_nreset SLCK Watchdog debug idle Timer ...
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Figure 9-2. System Controller Block Diagram (AT91SAM7S32/16) periph_irq[2..14] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq periph_nreset periph_nreset periph_nreset en BOD POR NRST RCOSC XIN OSC XOUT PLL PLLRC periph_nreset periph_nreset periph_clk[2] PA0-PA20 AT91SAM7S Series Summary 28 Interrupt Controller MCK Debug Unit ...
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Reset Controller The Reset Controller is based on a power-on reset cell and one brownout detector. It gives the status of the last reset, indicating whether power-up reset, a software reset, a user reset, a watchdog ...
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Clock Generator The Clock Generator embeds one low-power RC Oscillator, one Main Oscillator and one PLL with the following characteristics: • RC Oscillator ranges between 22 kHz and 42 kHz • Main Oscillator frequency ranges between 3 and 20 ...
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Figure 9-4. 9.4 Advanced Interrupt Controller • Controls the interrupt lines (nIRQ and nFIQ ARM Processor • Individually maskable and vectored interrupt sources – Source 0 is reserved for the Fast Interrupt Input (FIQ) – Source 1 is ...
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... Chip ID is 0x27090540 for AT91SAM7S64 Rev A – Chip ID is 0x27090543 for AT91SAM7S64 Rev B – Chip ID is 0x27090544 for AT91SAM7S64 Rev C – Chip ID is 0x27080342 for AT91SAM7S321 Rev A – Chip ID is 0x27080340 for AT91SAM7S32 Rev A – Chip ID is 0x27080341 for AT91SAM7S32 Rev B – ...
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Real-time Timer • 32-bit free-running counter with alarm running on prescaled SCLK • Programmable 16-bit prescaler for SLCK accuracy compensation 9.9 PIO Controller • One PIO Controller, controlling 32 I/O lines (21 for AT91SAM7S32/16) • Fully programmable through set/clear ...
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Peripherals 10.1 User Interface The User Peripherals are mapped in the 256 MBytes of address space between 0xF000 0000 and 0xFFFF EFFF. Each peripheral is allocated 16 Kbytes of address space. A complete memory map is provided in 10.2 ...
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Table 10-2. Peripheral Note: 10.3 Peripheral Multiplexing on PIO Lines The AT91SAM7S Series features one PIO controller, PIOA, that ...
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PIO Controller A Multiplexing Table 10-3. Multiplexing on PIO Controller A (AT91SAM7S512/256/128/64/321/161) PIO Controller A I/O Line Peripheral A PA0 PWM0 PA1 PWM1 PA2 PWM2 PA3 TWD PA4 TWCK PA5 RXD0 PA6 TXD0 PA7 RTS0 PA8 CTS0 PA9 DRXD ...
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Table 10-4. Multiplexing on PIO Controller A (AT91SAM7S32/16) PIO Controller A I/O Line Peripheral A PA0 PWM0 PA1 PWM1 PA2 PWM2 PA3 TWD PA4 TWCK PA5 RXD0 PA6 TXD0 PA7 RTS0 PA8 CTS0 PA9 DRXD PA10 DTXD PA11 NPCS0 PA12 ...
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Serial Peripheral Interface • Supports communication with external serial devices – Four chip selects with external decoder allow communication with – Serial memories, such as DataFlash – Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN ...
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ISO7816 Protocols for interfacing with smart cards – NACK handling, error counter with repetition and iteration limit • IrDA modulation and demodulation – Communication 115.2 Kbps • Test Modes ...
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PWM Controller • Four channels, one 16-bit counter per channel • Common clock generator, providing thirteen different clocks – One Modulo n counter providing eleven clocks – Two independent linear dividers working on modulo n counter outputs • Independent ...
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Package Drawings The SAM7S series devices are available in LQFP and QFN package types. 11.1 LQFP Packages Figure 11-1. 48-and 64-lead LQFP Package Drawing 6175IS–ATARM–30-Aug-10 AT91SAM7S Series Summary 41 ...
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Table 11-1. Symbol θ 1 θ 2 θ aaa bbb ccc ddd AT91SAM7S Series Summary 42 48-lead LQFP Package Dimensions (in ...
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Table 11-2. Symbol θ θ θ aaa bbb ccc ddd 6175IS–ATARM–30-Aug-10 AT91SAM7S Series Summary 64-lead LQFP Package Dimensions (in mm) Millimeter Min ...
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QFN Packages Figure 11-2. 48-pad QFN Package AT91SAM7S Series Summary 44 6175IS–ATARM–30-Aug-10 ...
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Table 11-3. Symbol aaa bbb ccc 6175IS–ATARM–30-Aug-10 AT91SAM7S Series Summary 48-pad QFN Package Dimensions (in mm) Millimeter Min Nom Max – – 090 – – 0.050 – 0.65 ...
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Figure 11-3. 64-pad QFN Package Drawing ll dimensions are in mm eference : JEDEC Drawing MO-220 AT91SAM7S Series Summary 46 6175IS–ATARM–30-Aug-10 ...
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Table 11-4. Symbol aaa bbb ccc 6175IS–ATARM–30-Aug-10 AT91SAM7S Series Summary 64-pad QFN Package Dimensions (in mm) Millimeter Min Nom Max – – 090 – – 0.05 – 0.65 ...
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... AT91SAM7S Ordering Information Table 12-1. AT91SAM7S Series Ordering Information MLR A Ordering Code MLR B Ordering Code AT91SAM7S16-AU AT91SAM7S16-MU AT91SAM7S161-AU AT91SAM7S32-AU-001 AT91SAM7S32B-AU AT91SAM7S32-MU AT91SAM7S32B-MU AT91SAM7S321-AU AT91SAM7S321-MU AT91SAM7S64B-AU – AT91SAM7S64B-MU AT91SAM7S128-AU-001 – AT91SAM7S128-MU AT91SAM7S256-AU-001 – AT91SAM7S256-MU AT91SAM7S512-AU AT91SAM7S512B-AU AT91SAM7S512-MU AT91SAM7S512B-MU AT91SAM7S Series Summary 48 MLR C Ordering Code – ...
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... Section 6. ”I/O Lines Considerations”, JTAG Port Pin, Test Pin, Erase Pin, updated. 6175IS–ATARM–30-Aug-10 AT91SAM7S Series Summary updated => => => AT91SAM7S321 changed in 3, QFN package information added USB Device port, Ping-pong Mode includes Isochronous endpoints. Reformatted Memories, Consolidated Memory Mapping in Reordered sub sections ...
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Doc. Rev Comments 6175GS “Features”,“Debug Unit (DBGU)” Communication” Section 7.4 ”Peripheral DMA Section 9. ”System Controller”, Section 9.1.1 ”Brownout Detector and Power-on Section 9.5 ”Debug Unit”, the list; B and SAM7S64 Rev B to the list. Section 12. ”AT91SAM7S Ordering ...
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