ATMEGA169P-16MCH Atmel, ATMEGA169P-16MCH Datasheet - Page 235
ATMEGA169P-16MCH
Manufacturer Part Number
ATMEGA169P-16MCH
Description
MCU AVR 16KB FLASH 16MHZ 64-VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA169PV-8AU.pdf
(395 pages)
Specifications of ATMEGA169P-16MCH
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRBFLY - KIT EVALUATION AVR BUTTERFLYATSTK502 - MOD EXPANSION AVR STARTER 500ATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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23.2.2
23.2.3
23.2.4
8018P–AVR–08/10
LCD Clock Sources
LCD Prescaler
LCD Memory
Figure 23-1. LCD Module Block Diagram
The LCD Controller can be clocked by an internal synchronous or an external asynchronous
clock source. The clock source clk
LCDCS bit in the LCDCRB Register is written to logic one, the clock source is taken from the
TOSC1 pin.
The clock source must be stable to obtain accurate LCD timing and hence minimize DC voltage
offset across LCD segments.
The prescaler consist of a 12-bit ripple counter and a 1- to 8-clock divider. The LCDPS2:0 bits
selects clk
If a finer resolution rate is required, the LCDCD2:0 bits can be used to divide the clock further by
1 to 8.
Output from the clock divider clk
The display memory is available through I/O Registers grouped for each common terminal.
When a bit in the display memory is written to one, the corresponding segment is energized (on),
and non-energized when a bit in the display memory is written to zero.
D
A
T
A
B
U
S
LCD
divided by 16, 64, 128, 256, 512, 1024, 2048, or 4096.
LCDCCR
LCDFRR
LCDCRA
LCDCRB
TOSC
LCDDR 18 -15
LCDDR 13 -10
clk
LCDDR 8 - 5
LCDDR 3 - 0
i/o
lcdcc3:0
0
1
lcdcs
Configuration
LATCH
array
Display
LCD_PS
clk
LCD
Contrast Controller/
LCD
Power Supply
lcdps2:0
lcdcd2:0
is used as clock source for the LCD timing.
is by default equal to the system clock, clk
MUX
25 x
4:1
Divide by 1 to 8
12-bit Prescaler
LCD_voltage_ok
Multiplexer
LCD Ouput
Decoder
Timing
Clock
LCD
clk
LCD_PS
LCD Buffer/
Driver
CAP
LCD
1/3 V
1/2 V
2/3 V
V
LCD
LCD
LCD
LCD
ATmega169P
Analog
Switch
Array
I/O
. When the
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
COM0
COM1
COM2
COM3
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
235
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