PIC18F85J90-I/PT Microchip Technology, PIC18F85J90-I/PT Datasheet
PIC18F85J90-I/PT
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PIC18F85J90-I/PT Summary of contents
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... Microcontrollers with LCD Driver © 2007 Microchip Technology Inc. PIC18F85J90 Family Data Sheet 64/80-Pin, High-Performance and nanoWatt Technology Preliminary DS39770B ...
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... Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... PIC18F85J90 32K 16384 © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY Low-Power Features: • Power-Managed modes: Run, Idle, Sleep • Run current down to 9 µA, typical • Idle current down to 2.5 µA, typical • Sleep current down to 0.1 µA, typical • ...
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... PIC18F85J90 FAMILY Pin Diagrams 64-Pin TQFP RE1/LCDBIAS2 1 RE0/LCDBIAS1 2 RG0/LCDBIAS0 3 RG1/TX2/CK2 4 RG2/RX2/DT2 LCAP RG3 LCAP MCLR 7 RG4/SEG26 DDCORE CAP 10 RF7/AN5/SS/SEG25 11 RF6/AN11/SEG24 12 RF5/AN10/CV /SEG23 REF 13 RF4/AN9/SEG22 14 RF3/AN8/SEG21 15 RF2/AN7/C1OUT/SEG20 16 Note 1: The CCP2 pin placement depends on the CCP2MX bit setting. DS39770B-page PIC18F63J90 PIC18F64J90 PIC18F65J90 Preliminary ...
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... DDCORE CAP 13 RF7/AN5/SS/SEG25 RF6/AN11/SEG24 14 RF5/AN10/CV /SEG23 15 REF RF4/AN9/SEG22 16 RF3/AN8/SEG21 17 RF2/AN7/C1OUT/SEG20 18 RH7/SEG43 19 RH6/SEG42 Note 1: The CCP2 pin placement depends on the CCP2MX bit setting. © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY PIC18F83J90 PIC18F84J90 PIC18F85J90 Preliminary RJ2/SEG34 59 RJ3/SEG35 58 RB0/INT0/SEG30 57 RB1/INT1/SEG8 56 RB2/INT2/SEG9 55 RB3/INT3/SEG10 54 RB4/KBI0/SEG11 ...
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... PIC18F85J90 FAMILY Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 7 2.0 Oscillator Configurations ............................................................................................................................................................ 29 3.0 Power-Managed Modes ............................................................................................................................................................. 37 4.0 Reset .......................................................................................................................................................................................... 45 5.0 Memory Organization ................................................................................................................................................................. 57 6.0 Flash Program Memory .............................................................................................................................................................. 81 7 Hardware Multiplier............................................................................................................................................................ 91 8.0 Interrupts .................................................................................................................................................................................... 93 9.0 I/O Ports ................................................................................................................................................................................... 109 10.0 Timer0 Module ......................................................................................................................................................................... 131 11.0 Timer1 Module ......................................................................................................................................................................... 135 12.0 Timer2 Module ......................................................................................................................................................................... 141 13 ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY Preliminary DS39770B-page 5 ...
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... PIC18F85J90 FAMILY NOTES: DS39770B-page 6 Preliminary © 2007 Microchip Technology Inc. ...
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... OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC18F85J90 family offer six different oscillator options, allowing users a range of choices in developing application hardware. These include: • Two Crystal modes, using crystals or ceramic resonators. • ...
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... Section 25.0 “Electrical Characteristics” for time-out periods. DS39770B-page 8 1.4 Details on Individual Family Members Devices in the PIC18F85J90 family are available in 64-pin and 80-pin packages. Block diagrams for the two groups are shown in Figure 1-1 and Figure 1-2. The devices are differentiated from each other in four ways: 1. ...
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... TABLE 1-1: DEVICE FEATURES FOR THE PIC18F85J90 FAMILY (64-PIN DEVICES) Features Operating Frequency Program Memory (Bytes) Program Memory (Instructions) Data Memory (Bytes) Interrupt Sources I/O Ports LCD Driver (available pixels to drive) Timers Capture/Compare/PWM Modules Serial Communications 10-bit Analog-to-Digital Module Resets (and Delays) ...
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... PIC18F85J90 FAMILY FIGURE 1-1: PIC18F6XJ90 (64-PIN) BLOCK DIAGRAM Table Pointer<21> inc/dec logic 21 20 Address Latch Program Memory (96 Kbytes) Data Latch 8 Table Latch ROM Latch Instruction Bus <16> Instruction Decode and Timing Power-up OSC2/CLKO Generation OSC1/CLKI INTRC Oscillator Oscillator Start-up Timer 8 MHz ...
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... RA6 and RA7 are only available as digital I/O in select oscillator modes. See Section 2.0 “Oscillator Configurations” for more information. 3: Brown-out Reset and Low-Voltage Detect functions are provided when the on-board voltage regulator is enabled. © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY Data Bus<8> Data Latch 8 8 Data Memory (2 ...
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... PIC18F85J90 FAMILY TABLE 1-3: PIC18F6XJ90 PINOUT I/O DESCRIPTIONS Pin Number Pin Name TQFP MCLR 7 OSC1/CLKI/RA7 39 OSC1 CLKI RA7 OSC2/CLKO/RA6 40 OSC2 CLKO RA6 RA0/AN0 24 RA0 AN0 RA1/AN1/SEG18 23 RA1 AN1 SEG18 RA2/AN2 REF RA2 AN2 V - REF RA3/AN3 REF RA3 AN3 V + REF RA4/T0CKI/SEG14 28 RA4 ...
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... Power Note 1: Default assignment for CCP2 when CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared. © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY Pin Buffer Type Type PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. ...
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... PIC18F85J90 FAMILY TABLE 1-3: PIC18F6XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RC0/T1OSO/T13CKI 30 RC0 T1OSO T13CKI RC1/T1OSI/CCP2/SEG32 29 RC1 T1OSI (1) CCP2 SEG32 RC2/CCP1/SEG13 33 RC2 CCP1 SEG13 RC3/SCK/SCL/SEG17 34 RC3 SCK SCL SEG17 RC4/SDI/SDA/SEG16 35 RC4 SDI SDA SEG16 RC5/SDO/SEG12 36 RC5 SDO SEG12 ...
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... Schmitt Trigger input with CMOS levels I = Input P = Power Note 1: Default assignment for CCP2 when CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared. © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY Pin Buffer Type Type PORTD is a bidirectional I/O port. I/O ST Digital I/O. O Analog SEG0 output for LCD ...
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... PIC18F85J90 FAMILY TABLE 1-3: PIC18F6XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RE0/LCDBIAS1 2 RE0 LCDBIAS1 RE1/LCDBIAS2 1 RE1 LCDBIAS2 LCDBIAS3 64 RE3/COM0 63 RE3 COM0 RE4/COM1 62 RE4 COM1 RE5/COM2 61 RE5 COM2 RE6/COM3 60 RE6 COM3 RE7/CCP2/SEG31 59 RE7 (2) CCP2 SEG31 Legend: TTL = TTL compatible input ...
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... Schmitt Trigger input with CMOS levels I = Input P = Power Note 1: Default assignment for CCP2 when CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared. © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY Pin Buffer Type Type PORTF is a bidirectional I/O port. I/O ST Digital I/O. I Analog Analog input 6 ...
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... PIC18F85J90 FAMILY TABLE 1-3: PIC18F6XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RG0/LCDBIAS0 3 RG0 LCDBIAS0 RG1/TX2/CK2 4 RG1 TX2 CK2 RG2/RX2/DT2 LCAP RG2 RX2 DT2 V 1 LCAP RG3 LCAP RG3 V 2 LCAP RG4/SEG26 8 RG4 SEG26 V 9, 25, 41 26, 38 ENVREG DDCORE ...
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... Input P = Power Note 1: Default assignment for CCP2 when CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared. © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY Pin Buffer Type Type I ST Master Clear (input) or programming voltage (input). This pin is an active-low Reset to the device. ...
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... PIC18F85J90 FAMILY TABLE 1-4: PIC18F8XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RB0/INT0/SEG30 58 RB0 INT0 SEG30 RB1/INT1/SEG8 57 RB1 INT1 SEG8 RB2/INT2/SEG9 56 RB2 INT2 SEG9 RB3/INT3/SEG10 55 RB3 INT3 SEG10 RB4/KBI0/SEG11 54 RB4 KBI0 SEG11 RB5/KBI1/SEG29 53 RB5 KBI1 SEG29 RB6/KBI2/PGC 52 RB6 KBI2 ...
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... Schmitt Trigger input with CMOS levels I = Input P = Power Note 1: Default assignment for CCP2 when CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared. © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY Pin Buffer Type Type PORTC is a bidirectional I/O port. I/O ST Digital I/O. O — ...
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... PIC18F85J90 FAMILY TABLE 1-4: PIC18F8XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RD0/SEG0 72 RD0 SEG0 RD1/SEG1 69 RD1 SEG1 RD2/SEG2 68 RD2 SEG2 RD3/SEG3 67 RD3 SEG3 RD4/SEG4 66 RD4 SEG4 RD5/SEG5 65 RD5 SEG5 RD6/SEG6 64 RD6 SEG6 RD7/SEG7 63 RD7 SEG7 Legend: TTL = TTL compatible input ...
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... Schmitt Trigger input with CMOS levels I = Input P = Power Note 1: Default assignment for CCP2 when CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared. © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY Pin Buffer Type Type PORTE is a bidirectional I/O port. I/O ST Digital I/O. I Analog BIAS1 input for LCD ...
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... PIC18F85J90 FAMILY TABLE 1-4: PIC18F8XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RF1/AN6/C2OUT/SEG19 23 RF1 AN6 C2OUT SEG19 RF2/AN7/C1OUT/SEG20 18 RF2 AN7 C1OUT SEG20 RF3/AN8/SEG21 17 RF3 AN8 SEG21 RF4/AN9/SEG22 16 RF4 AN9 SEG22 RF5/AN10/CV /SEG23 15 REF RF5 AN10 CV REF SEG23 RF6/AN11/SEG24 14 RF6 ...
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... Schmitt Trigger input with CMOS levels I = Input P = Power Note 1: Default assignment for CCP2 when CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared. © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY Pin Buffer Type Type PORTG is a bidirectional I/O port. I/O ST Digital I/O. I Analog BIAS0 input for LCD ...
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... PIC18F85J90 FAMILY TABLE 1-4: PIC18F8XJ90 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RH0/SEG47 79 RH0 SEG47 RH1/SEG46 80 RH1 SEG46 RH2/SEG45 1 RH2 SEG45 RH3/SEG44 2 RH3 SEG44 RH4/SEG40 22 RH4 SEG40 RH5/SEG41 21 RH5 SEG41 RH6/SEG42 20 RH6 SEG42 RH7/SEG43 19 RH7 SEG43 Legend: TTL = TTL compatible input ...
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... I = Input P = Power Note 1: Default assignment for CCP2 when CCP2MX Configuration bit is set. 2: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared. © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY Pin Buffer Type Type PORTJ is a bidirectional I/O port. I/O ST Digital I/O. I/O ST Digital I/O ...
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... PIC18F85J90 FAMILY NOTES: DS39770B-page 28 Preliminary © 2007 Microchip Technology Inc. ...
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... OSCILLATOR CONFIGURATIONS 2.1 Oscillator Types The PIC18F85J90 family of devices can be operated in six different oscillator modes High-Speed Crystal/Resonator 2. HSPLL High-Speed Crystal/Resonator with Software PLL Control 3. EC External Clock with F OSC 4. ECPLL External Clock with Software PLL Control 5. INTOSC Internal Fast RC (8 MHz) oscillator 6 ...
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... PIC18F85J90 FAMILY 2.2 Control Registers The OSCCON register (Register 2-1) controls the main aspects of the device clock’s operation. It selects the oscillator type to be used, which of the power-managed modes to invoke and the output frequency of the INTOSC source. It also provides status on the oscillators ...
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... Monitor. The internal oscillator block is discussed in more detail in Section 2.5 “Internal Oscillator Block”. The PIC18F85J90 family includes features that allow the device clock source to be switched from the main oscillator, chosen by device configuration, to one of the alternate clock sources. When an alternate clock source is enabled, various power-managed operating modes are available ...
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... SCS1:SCS0, at any given time, depending on the setting of FOSC2. 2.3.2 OSCILLATOR TRANSITIONS PIC18F85J90 family devices contain circuitry to prevent clock “glitches” when switching between clock sources. A short pause in the device clock occurs dur- ing the clock switch. The length of this pause is the sum of two cycles of the old clock source and three to four cycles of the new clock source ...
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... AN943, “Practical PIC Oscillator Analysis and Design” • AN949, “Making Your Oscillator Work” See the notes following Table 2-2 for additional information. © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY TABLE 2-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Crystal Osc Type Freq. ...
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... PIC18F85J90 FAMILY 2.4.2 EXTERNAL CLOCK INPUT (EC MODES) The EC and ECPLL Oscillator modes require an exter- nal clock source to be connected to the OSC1 pin. There is no oscillator start-up time required after a Power-on Reset or after an exit from Sleep mode. In the EC Oscillator mode, the oscillator frequency divided available on the OSC2 pin ...
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... Internal Oscillator Block The PIC18F85J90 family of devices includes an internal oscillator block which generates two different clock signals; either can be used as the microcontroller’s clock source. This may eliminate the need for an external oscillator circuit on the OSC1 and/or OSC2 pins. The main output is the Fast RC oscillator, or INTOSC MHz clock source which can be used to directly drive the device clock ...
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... PIC18F85J90 FAMILY 2.6 Effects of Power-Managed Modes on the Various Clock Sources When PRI_IDLE mode is selected, the designated pri- mary oscillator continues to run without interruption. For all other power-managed modes, the oscillator using the OSC1 pin is disabled. The OSC1 pin (and OSC2 pin if used by the oscillator) will stop oscillating. ...
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... POWER-MANAGED MODES The PIC18F85J90 family devices provide the ability to manage power consumption by simply managing clock- ing to the CPU and the peripherals. In general, a lower clock frequency and a reduction in the number of circuits being clocked constitutes lower consumed power. For the sake of managing power in an application, there are three primary modes of operation: • ...
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... PIC18F85J90 FAMILY 3.1.3 CLOCK TRANSITIONS AND STATUS INDICATORS The length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Two bits indicate the current clock source and its ...
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... These intervals are not shown to scale. OST OSC PLL © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY On transitions from SEC_RUN mode to PRI_RUN mode, the peripherals and CPU continue to be clocked from the Timer1 oscillator while the primary clock is started. When the primary clock becomes ready, a clock switch back to the primary clock occurs (see Figure 3-2) ...
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... PIC18F85J90 FAMILY 3.2.3 RC_RUN MODE In RC_RUN mode, the CPU and peripherals are clocked from the internal oscillator; the primary clock is shut down. This mode provides the best power conser- vation of all the Run modes while still executing code. It works well for user applications which are not highly timing sensitive or do not require high-speed clocks at all times ...
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... These intervals are not shown to scale. OST OSC PLL © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY 3.4 Idle Modes The Idle modes allow the controller’s CPU to be selectively shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption. If the IDLEN bit is set to a ‘ ...
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... PIC18F85J90 FAMILY 3.4.1 PRI_IDLE MODE This mode is unique among the three low-power Idle modes, in that it does not disable the primary device clock. For timing sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to “ ...
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... CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay. © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY 3.5.2 EXIT BY WDT TIME-OUT A WDT time-out will cause different actions depending on which power-managed mode the device is in when the time-out occurs ...
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... PIC18F85J90 FAMILY NOTES: DS39770B-page 44 Preliminary © 2007 Microchip Technology Inc. ...
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... RESET The PIC18F85J90 family of devices differentiate between various kinds of Reset: a) Power-on Reset (POR) b) MCLR Reset during normal operation c) MCLR Reset during power-managed modes d) Watchdog Timer (WDT) Reset (during execution) e) Brown-out Reset (BOR) f) RESET Instruction g) Stack Full Reset h) Stack Underflow Reset ...
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... PIC18F85J90 FAMILY REGISTER 4-1: RCON: RESET CONTROL REGISTER R/W-0 U-0 U-0 IPEN — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16XXXX Compatibility mode) bit 6-5 Unimplemented: Read as ‘ ...
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... To capture multiple events, the user manually resets the bit to ‘1’ in software following any Power-on Reset. 4.4 Brown-out Reset (BOR) The PIC18F85J90 family of devices incorporates a simple BOR function when the internal regulator is enabled (ENVREG pin is tied The voltage reg- DD ...
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... Reset process. The PWRT is always enabled. The main function is to ensure that the device voltage is stable before code is executed. The Power-up Timer (PWRT) of the PIC18F85J90 fam- ily devices is an 11-bit counter which uses the INTRC source as the clock input. This yields an approximate time interval of 2048 ...
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... TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET FIGURE 4-6: SLOW RISE TIME (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY T PWRT , V RISE > 3. PWRT Preliminary ): CASE PWRT ...
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... PIC18F85J90 FAMILY 4.6 Reset State of Registers Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a “Reset state” depending on the type of Reset that occurred. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation ...
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... Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read as ‘0’. © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY MCLR Resets Power-on Reset, WDT Reset Brown-out Reset ...
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... PIC18F85J90 FAMILY TABLE 4-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices FSR1H PIC18F6XJ90 PIC18F8XJ90 FSR1L PIC18F6XJ90 PIC18F8XJ90 BSR PIC18F6XJ90 PIC18F8XJ90 INDF2 PIC18F6XJ90 PIC18F8XJ90 POSTINC2 PIC18F6XJ90 PIC18F8XJ90 POSTDEC2 PIC18F6XJ90 PIC18F8XJ90 PREINC2 PIC18F6XJ90 PIC18F8XJ90 PLUSW2 PIC18F6XJ90 PIC18F8XJ90 FSR2H PIC18F6XJ90 PIC18F8XJ90 FSR2L ...
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... Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read as ‘0’. © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY MCLR Resets Power-on Reset, WDT Reset Brown-out Reset ...
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... PIC18F85J90 FAMILY TABLE 4-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices IPR3 PIC18F6XJ90 PIC18F8XJ90 PIR3 PIC18F6XJ90 PIC18F8XJ90 PIE3 PIC18F6XJ90 PIC18F8XJ90 IPR2 PIC18F6XJ90 PIC18F8XJ90 PIR2 PIC18F6XJ90 PIC18F8XJ90 PIE2 PIC18F6XJ90 PIC18F8XJ90 IPR1 PIC18F6XJ90 PIC18F8XJ90 PIR1 PIC18F6XJ90 PIC18F8XJ90 PIE1 PIC18F6XJ90 PIC18F8XJ90 OSCTUNE ...
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... Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read as ‘0’. © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY MCLR Resets Power-on Reset, WDT Reset Brown-out Reset ...
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... PIC18F85J90 FAMILY TABLE 4-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices CCPR2L PIC18F6XJ90 PIC18F8XJ90 CCP2CON PIC18F6XJ90 PIC18F8XJ90 SPBRG2 PIC18F6XJ90 PIC18F8XJ90 RCREG2 PIC18F6XJ90 PIC18F8XJ90 TXREG2 PIC18F6XJ90 PIC18F8XJ90 TXSTA2 PIC18F6XJ90 PIC18F8XJ90 RCSTA2 PIC18F6XJ90 PIC18F8XJ90 Legend unchanged unknown unimplemented bit, read as ‘0’ value depends on condition. ...
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... Accessing a location between the upper boundary of the physically implemented memory and the 2-Mbyte address will return all ‘0’s (a NOP instruction). The entire PIC18F85J90 family offers a range of on-chip Flash program memory sizes, from 8 Kbytes (up to 4,096 single-word instructions Kbytes (32,768 ...
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... Words, CONFIG3, are used; CONFIG4 is reserved. The actual addresses of the Flash Configuration Word for devices in the PIC18F85J90 family are shown in Table 5-1. Their location in the memory map is shown with the other memory vectors in Figure 5-2. Additional details on the device Configuration Words are provided in Section 22.1 “ ...
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... Microchip Technology Inc. PIC18F85J90 FAMILY The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer, STKPTR. The stack space is not part of either program or data space. The Stack Pointer is readable and writable and the address on the top of the stack is readable and writable through the Top-of-Stack Special Function Registers ...
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... PIC18F85J90 FAMILY 5.1.4.2 Return Stack Pointer (STKPTR) The STKPTR register (Register 5-1) contains the Stack Pointer value, the STKFUL (Stack Full) status bit and the STKUNF (Stack Underflow) status bits. The value of the Stack Pointer can be 0 through 31. The Stack Pointer increments before values are pushed onto the stack and decrements after values are popped off the stack ...
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... SUB1 RETURN FAST ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY 5.1.6 LOOK-UP TABLES IN PROGRAM MEMORY There may be programming situations that require the creation of data structures, or look-up tables, in program memory. For PIC18 devices, look-up tables can be implemented in two ways: • ...
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... PIC18F85J90 FAMILY 5.2 PIC18 Instruction Cycle 5.2.1 CLOCKING SCHEME The microcontroller clock input, whether from an internal or external source, is internally divided by four to generate four non-overlapping quadrature clocks (Q1, Q2, Q3 and Q4). Internally, the program counter is incremented on every Q1; the instruction is fetched from the program memory and latched into the Instruction Register (IR) during Q4 ...
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... ADDWF © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY The CALL and GOTO instructions have the absolute program memory address embedded into the instruc- tion. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. The word address is written to PC< ...
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... PIC18F85J90 FAMILY 5.3 Data Memory Organization Note: The operation of some aspects of data memory are changed when the PIC18 extended instruction set is enabled. See Section 5.6 “Data Memory and the Extended Instruction Set” for more information. The data memory in PIC18 devices is implemented as static RAM ...
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... FFh 00h = 0011 Bank 3 FFh 00h = 0100 Bank 1110 Bank 14 FFh 00h = 1111 Bank 15 FFh © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY Data Memory Map 000h Access RAM 05Fh 060h GPR 0FFh 100h GPR 1FFh 200h GPR 2FFh 300h GPR 3FFh ...
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... PIC18F85J90 FAMILY FIGURE 5-7: DATA MEMORY MAP FOR PIC18FX5J90 DEVICES BSR<3:0> 00h = 0000 Bank 0 FFh 00h = 0001 Bank 1 FFh 00h = 0010 Bank 2 FFh 00h = 0011 Bank 3 FFh 00h = 0100 Bank 4 FFh 00h = 0101 Bank 5 FFh 00h = 0110 Bank 6 FFh 00h = 0111 ...
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... When ‘a’ is equal to ‘1’, the instruction uses the BSR and the 8-bit address included in the opcode for the data memory address. When ‘a’ is ‘0’, © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY Data Memory 000h 7 00h ...
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... RAM. SFRs start at the top of data memory (FFFh) and extend downward to occupy more than the top half of Bank 15 (F60h to FFFh). A list of these registers is given in Table 5-2 and Table 5-3. TABLE 5-2: SPECIAL FUNCTION REGISTER MAP FOR PIC18F85J90 FAMILY DEVICES Address Name Address Name ...
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... TABLE 5-3: PIC18F85J90 FAMILY REGISTER FILE SUMMARY Filename Bit 7 Bit 6 TOSU — — TOSH Top-of-Stack High Byte (TOS<15:8>) TOSL Top-of-Stack Low Byte (TOS<7:0>) STKPTR STKFUL STKUNF PCLATU — — bit 21 PCLATH Holding Register for PC<15:8> PCL PC Low Byte (PC<7:0>) TBLPTRU — ...
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... PIC18F85J90 FAMILY TABLE 5-3: PIC18F85J90 FAMILY REGISTER FILE SUMMARY (CONTINUED) Filename Bit 7 Bit 6 TMR0H Timer0 Register High Byte TMR0L Timer0 Register Low Byte T0CON TMR0ON T08BIT T0CS OSCCON IDLEN IRCF2 IRCF1 LCDREG — CPEN BIAS2 WDTCON REGSLP — RCON IPEN — ...
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... TABLE 5-3: PIC18F85J90 FAMILY REGISTER FILE SUMMARY (CONTINUED) Filename Bit 7 Bit 6 SPBRG1 EUSART Baud Rate Generator RCREG1 EUSART Receive Register TXREG1 EUSART Transmit Register TXSTA1 CSRC TX9 TXEN RCSTA1 SPEN RX9 SREN LCDPS WFT BIASMD LCDA LCDSE0 SE07 SE06 SE05 LCDCON ...
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... PIC18F85J90 FAMILY TABLE 5-3: PIC18F85J90 FAMILY REGISTER FILE SUMMARY (CONTINUED) Filename Bit 7 Bit 6 (2) PORTJ RJ7 RJ6 (2) PORTH RH7 RH6 PORTG RDPU REPU RJPU PORTF RF7 RF6 PORTE RE7 RE6 PORTD RD7 RD6 PORTC RC7 RC6 PORTB RB7 RB6 (5) (5) PORTA ...
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... For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register. © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY register then reads back as ‘000u u1uu’ recom- mended, therefore, that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions are used to alter the ...
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... PIC18F85J90 FAMILY 5.4 Data Addressing Modes Note: The execution of some instructions in the core PIC18 instruction set are changed when the PIC18 extended instruction set is enabled. See Section 5.6 “Data Memory and the Extended Instruction Set” for more information. While the program memory can be addressed in only one way – ...
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... FCCh will be added to that of the W register and stored back in FCCh. © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY the SFR space but are not physically implemented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. A read from INDF1, for example, reads the data at the address indicated by FSR1H:FSR1L ...
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... PIC18F85J90 FAMILY 5.4.3.2 FSR Registers and POSTINC, POSTDEC, PREINC and PLUSW In addition to the INDF operand, each FSR register pair also has four additional indirect operands. Like INDF, these are “virtual” registers that cannot be indirectly read or written to. Accessing these registers actually accesses the associated FSR register pair, but also performs a specific action on its stored value ...
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... Address Pointer specified by FSR2. The offset and the contents of FSR2 are added to obtain the target address of the operation. © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY 5.6.2 INSTRUCTIONS AFFECTED BY INDEXED LITERAL OFFSET MODE Any of the core PIC18 instructions that can use Direct Addressing are potentially affected by the Indexed Literal Offset Addressing mode ...
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... PIC18F85J90 FAMILY FIGURE 5-10: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF (Opcode: 0010 01da ffff ffff) When and f 60h: The instruction executes in Direct Forced mode. ‘f’ is interpreted as a location in the Access RAM between 060h and FFFh ...
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... BSR. F60h FFFh © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY Remapping of the Access Bank applies only to opera- tions using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit is ‘1’) will continue to use Direct Addressing as before. Any Indirect or ...
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... PIC18F85J90 FAMILY NOTES: DS39770B-page 80 Preliminary © 2007 Microchip Technology Inc. ...
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... Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY 6.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...
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... PIC18F85J90 FAMILY FIGURE 6-2: TABLE WRITE OPERATION (1) Table Pointer TBLPTRU TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer actually points to one of 64 holding registers, the address of which is determined by TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in Section 6.5 “Writing to Flash Program Memory”. ...
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... Initiates a program memory erase cycle or write cycle (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software Write cycle is complete bit 0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY R/W-0 R/W-x R/W-0 FREE WRERR WREN S = Set only bit (cannot be cleared in software) ‘ ...
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... PIC18F85J90 FAMILY 6.2.2 TABLE LATCH REGISTER (TABLAT) The Table Latch (TABLAT 8-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. 6.2.3 TABLE POINTER REGISTER (TBLPTR) The Table Pointer (TBLPTR) register addresses a byte within the program memory ...
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... TABLAT, W MOVWF WORD_ODD © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. Figure 6-4 shows the interface between the internal program memory and the TABLAT ...
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... PIC18F85J90 FAMILY 6.4 Erasing Flash Program Memory The minimum erase block is 512 words or 1024 bytes. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be Bulk Erased. Word erase in the Flash array is not supported. When initiating an erase sequence from the micro- controller itself, a block of 1024 bytes of program memory is erased ...
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... The on-chip timer controls the write time. The write/erase voltages are generated by an on-chip charge pump, rated to operate over the voltage range of the device. Note 1: Unlike previous PIC of the PIC18F85J90 family do not reset the holding registers after a write occurs. The holding registers must be cleared or overwritten sequence. ...
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... PIC18F85J90 FAMILY EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY MOVLW CODE_ADDR_UPPER MOVWF TBLPTRU MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL ERASE_BLOCK BSF EECON1, WREN BSF EECON1, FREE BCF INTCON, GIE MOVLW 55h MOVWF EECON2 MOVLW 0AAh MOVWF EECON2 BSF EECON1, WR BSF ...
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... EECON1 — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during program memory access. © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY 6.6 Flash Program Operation During Code Protection See Section 22.6 “Program Verification and Code Protection” for details on code protection of Flash program memory ...
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... PIC18F85J90 FAMILY NOTES: DS39770B-page 90 Preliminary © 2007 Microchip Technology Inc. ...
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... Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY EXAMPLE 7- UNSIGNED MULTIPLY ROUTINE MOVF ARG1 MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL EXAMPLE 7-2: ...
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... PIC18F85J90 FAMILY Example 7-3 shows the sequence unsigned multiplication. Equation 7-1 shows the algorithm that is used. The 32-bit result is stored in four registers (RES3:RES0). EQUATION 7- UNSIGNED MULTIPLICATION ALGORITHM RES3:RES0 = ARG1H:ARG1L ARG2H:ARG2L = (ARG1H ARG2H 2 8 (ARG1H ARG2L 2 8 (ARG1L ARG2H 2 (ARG1L ARG2L) EXAMPLE 7-3: ...
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... INTERRUPTS Members of the PIC18F85J90 family of devices have multiple interrupt sources and an interrupt priority feature that allows most interrupt sources to be assigned a high priority level or a low priority level. The high priority interrupt vector is at 0008h and the low priority interrupt vector is at 0018h. High priority inter- rupt events will interrupt any low priority interrupts that may be in progress ...
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... PIC18F85J90 FAMILY FIGURE 8-1: PIC18F85J90 FAMILY INTERRUPT LOGIC PIR1<6:3,1:0> PIE1<6:3,1:0> IPR1<6:3,1:0> PIR2<7:6,3:1> PIE2<7:6 3:1> IPR2<7:6,3:1> PIR3<6:4,2:1> PIE3<6:4,2:1> IPR3<6:4,2:1> High Priority Interrupt Generation Low Priority Interrupt Generation PIR1<6:3,1:0> PIE1<6:3,1:0> IPR1<6:3,1:0> PIR2<7:6,3:1> PIE2<7:6,3:1> IPR2<7:6,3:1> PIR3<6:4,2:1> PIE3<6:4,2:1> IPR3<6:4,2:1> DS39770B-page 94 TMR0IF TMR0IE TMR0IP RBIF RBIE ...
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... Note 1: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit ...
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... PIC18F85J90 FAMILY REGISTER 8-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 R/W-1 RBPU INTEDG0 INTEDG1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values ...
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... Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY R/W-0 R/W-0 R/W-0 ...
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... PIC18F85J90 FAMILY 8.2 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Request (Flag) registers (PIR1, PIR2, PIR3). REGISTER 8-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 ...
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... TMR3IF: TMR3 Overflow Interrupt Flag bit 1 = TMR3 register overflowed (must be cleared in software TMR3 register did not overflow bit 0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY U-0 R/W-0 R/W-0 — BCLIF LVDIF U = Unimplemented bit, read as ‘0’ ...
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... PIC18F85J90 FAMILY REGISTER 8-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 U-0 R/W-0 R-0 — LCDIF RC2IF bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 Unimplemented: Read as ‘0’ bit 6 LCDIF: LCD Interrupt Flag bit (valid when Type-B waveform with Non-Static mode is selected) ...
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... Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY R/W-0 R/W-0 U-0 TX1IE SSPIE — ...
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... PIC18F85J90 FAMILY REGISTER 8-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 R/W-0 U-0 OSCFIE CMIE — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 CMIE: Comparator Interrupt Enable bit ...
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... Disabled bit 1 CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY R-0 U-0 R/W-0 TX2IE — CCP2IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
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... PIC18F85J90 FAMILY 8.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Priority registers (IPR1, IPR2, IPR3). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set ...
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... High priority 0 = Low priority bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY U-0 R/W-1 R/W-1 — BCLIP LVDIP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
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... PIC18F85J90 FAMILY REGISTER 8-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 U-0 R/W-0 R-0 — LCDIP RC2IP bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 Unimplemented: Read as ‘0’ bit 6 LCDIP: LCD Interrupt Priority bit (valid when Type-B waveform with Non-Static mode is selected) ...
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... For details of bit operation, see Register 4-1. bit 1 POR: Power-on Reset Status bit For details of bit operation, see Register 4-1. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register 4-1. © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY R/W-1 R-1 R Unimplemented bit, read as ‘0’ ...
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... PIC18F85J90 FAMILY 8.6 INTx Pin Interrupts External interrupts on the RB0/INT0, RB1/INT1, RB2/INT2 and RB3/INT3 pins are edge-triggered. If the corresponding INTEDGx bit in the INTCON2 register is set (= 1), the interrupt is triggered by a rising edge; if the bit is clear, the trigger is on the falling edge. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit, INTxIF, is set ...
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... EN RD PORT Note 1: I/O pins have diode protection © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY 9.1 I/O Port Pin Capabilities When developing an application, the capabilities of the port pins must be considered. Outputs on some pins have higher output drive strength than others. Similarly, some pins can tolerate higher than V 9 ...
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... PIC18F85J90 FAMILY TABLE 9-2: OUTPUT DRIVE LEVELS FOR VARIOUS PORTS Low Medium PORTA<5:0> PORTD PORTA<7:6> PORTF PORTE PORTB (1) PORTG PORTJ PORTC (1) PORTH Note 1: Not available on 64-pin devices. 9.1.3 PULL-UP CONFIGURATION Four of the I/O ports (PORTB, PORTD, PORTE and PORTJ) implement configurable weak pull-ups on all pins ...
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... Shaded cells are not used by PORTA. Note 1: These bits are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read as ‘X’. © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY I/O I/O Type O DIG LATA< ...
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... PIC18F85J90 FAMILY 9.3 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bidirectional port. The corresponding Data Direction and Output Latch registers are TRISB and LATB. All pins on PORTB are digital only and tolerate voltages up to 5.5V. EXAMPLE 9-2: INITIALIZING PORTB ...
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... O = Output Input, ANA = Analog Signal, DIG = Digital Output Schmitt Trigger Buffer Input, TTL = TTL Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY I/O I/O Type ...
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... PIC18F85J90 FAMILY TABLE 9-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Name Bit 7 Bit 6 PORTB RB7 RB6 LATB LATB7 LATB6 TRISB TRISB7 TRISB6 INTCON GIE/GIEH PEIE/GIEL TMR0IE INTCON2 RBPU INTEDG0 INTEDG1 INTCON3 INT2IP INT1IP LCDSE1 SE15 SE14 LCDSE3 SE31 SE30 Legend: Shaded cells are not used by PORTB. ...
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... Note: These pins are configured as digital inputs on any device Reset. © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY The contents of the TRISC register are affected by peripheral overrides. Reading TRISC always returns the current contents, even though a peripheral device may be overriding one or more of the pins. ...
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... PIC18F85J90 FAMILY TABLE 9-7: PORTC FUNCTIONS TRIS Pin Name Function I/O Setting RC0/T1OSO/ RC0 O 0 T13CKI I 1 T1OSO O x T13CKI I 1 RC1/T1OSI/ RC1 O 0 CCP2/SEG32 I 1 T1OSI I x (1) CCP2 SEG32 O x RC2/CCP1/ RC2 O 0 SEG13 I 1 CCP1 SEG13 O x RC3/SCK/SCL/ RC3 ...
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... SE22 LCDSE3 SE31 SE30 (1) (1) LCDSE4 SE39 SE38 Legend: Shaded cells are not used by PORTC. Note 1: Unimplemented on 64-pin devices, read as ‘0’. © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 RC5 RC4 RC3 RC2 LATC5 LATCB4 LATC3 LATC2 ...
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... PIC18F85J90 FAMILY 9.5 PORTD, TRISD and LATD Registers PORTD is an 8-bit wide, bidirectional port. The corresponding Data Direction and Output Latch registers are TRISD and LATD. All pins on PORTD are digital only and tolerate voltages up to 5.5V. All pins on PORTD are implemented with Schmitt Trigger input buffers ...
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... TRISD7 TRISD6 PORTG RDPU REPU LCDSE0 SE7 SE6 Legend: Shaded cells are not used by PORTD. Note 1: Unimplemented on 64-pin devices, read as ‘0’. © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY I/O I/O Type O DIG LATD<0> data output PORTD<0> data input. O ANA LCD segment 0 output; disables all other pin functions. ...
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... PIC18F85J90 FAMILY 9.6 PORTE, TRISE and LATE Registers PORTE is a 7-bit wide, bidirectional port. The corresponding Data Direction and Output Latch registers are TRISE and LATE. All pins on PORTE are digital only and tolerate voltages up to 5.5V. All pins on PORTE are implemented with Schmitt Trigger input buffers ...
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... SPIOD CCP2OD CCP1OD LCDCON LCDEN SLPEN LCDSE3 SE31 SE30 Legend: Shaded cells are not used by PORTE. Note 1: Unimplemented on 64-pin devices, read as ‘0’. © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY I/O I/O Type O DIG LATE<0> data output PORTE<0> data input. I ANA LCD module bias voltage input ...
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... PIC18F85J90 FAMILY 9.7 PORTF, LATF and TRISF Registers PORTF is a 7-bit wide, bidirectional port. The corresponding Data Direction and Output Latch registers are TRISF and LATF. All pins on PORTF are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. ...
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... O = Output Input, ANA = Analog Signal, DIG = Digital Output Schmitt Trigger Buffer Input, TTL = TTL Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY I/O I/O Type ...
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... PIC18F85J90 FAMILY TABLE 9-15: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF Name Bit 7 Bit 6 PORTF RF7 RF6 LATF LATF7 LATF6 TRISF TRISF7 TRISF6 ADCON1 — — CMCON C2OUT C1OUT CVRCON CVREN CVROE LCDSE2 SE23 SE22 LCDSE3 SE31 SE30 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTF. ...
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... TRIS register. This allows read-modify-write of the TRIS register without concern due to peripheral overrides. © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY Although the port itself is only five bits wide, the PORTG<7:5> bits are still implemented to control the weak pull-ups on the I/O ports associated with PORTD, PORTE and PORTJ ...
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... PIC18F85J90 FAMILY TABLE 9-16: PORTG FUNCTIONS TRIS Pin Name Function Setting RG0/LCDBIAS0 RG0 0 1 LCDBIAS0 x RG1/TX2/CK2 RG1 0 1 TX2 1 CK2 1 1 RG2/RX2/DT2/V RG2 0 1 LCAP 1 RX2 1 DT2 LCAP x RG3/V 2 RG3 0 LCAP LCAP RG4/SEG26 RG4 0 1 SEG26 x Legend Output Input, ANA = Analog Signal, DIG = Digital Output Schmitt Trigger Buffer Input Don’ ...
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... All PORTH pins are multiplexed with LCD segment drives controlled by the LCDSE5 register. I/O port functions are only available when the segments are disabled. © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY EXAMPLE 9-8: INITIALIZING PORTH CLRF PORTH ; Initialize PORTH by ...
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... PIC18F85J90 FAMILY TABLE 9-18: PORTH FUNCTIONS TRIS Pin Name Function Setting RH0/SEG47 RH0 0 1 SEG47 x RH1/SEG46 RH1 0 1 SEG46 x RH2/SEG45 RH2 0 1 SEG45 x RH3/SEG44 RH3 0 1 SEG44 x RH4/SEG40 RH4 0 1 SEG40 x RH5/SEG41 RH5 0 1 SEG41 x RH6/SEG42 RH6 0 1 SEG42 x RH7/SEG43 RH7 ...
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... Microchip Technology Inc. PIC18F85J90 FAMILY Each of the PORTJ pins has a weak internal pull-up. The pull-ups are provided to keep the inputs at a known state for the external memory interface while powering up. A single control bit can turn off all the pull-ups. This is performed by clearing bit RJPU (PORTG< ...
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... PIC18F85J90 FAMILY TABLE 9-20: PORTJ FUNCTIONS TRIS Pin Name Function Setting RJ0 RJ0 0 1 RJ1/SEG33 RJ1 0 1 SEG33 x RJ2/SEG34 RJ2 0 1 SEG34 x RJ3/SEG35 RJ3 0 1 SEG35 x RJ4/SEG39 RJ4 0 1 SEG39 x RJ5/SEG38 RJ5 0 1 SEG38 x RJ6/SEG37 RJ6 0 1 SEG37 x RJ7/SEG36 RJ7 0 1 SEG36 ...
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... Prescale value 000 = 1:2 Prescale value © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY The T0CON register (Register 10-1) controls all aspects of the module’s operation, including the prescale selection both readable and writable. A simplified block diagram of the Timer0 module in 8-bit mode is shown in Figure 10-1 ...
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... PIC18F85J90 FAMILY 10.1 Timer0 Operation Timer0 can operate as either a timer or a counter. The mode is selected with the T0CS bit (T0CON<5>). In Timer mode (T0CS = 0), the module increments on every clock by default unless a different prescaler value is selected (see Section 10.3 “Prescaler”). If the TMR0 register is written to, the increment is inhibited for the following two instruction cycles ...
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... RA6/RA7 and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default clock source (FOSC2 Configuration bit = 0); otherwise, they are disabled and these bits read as ‘0’. © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY 10.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control and can be changed “ ...
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... PIC18F85J90 FAMILY NOTES: DS39770B-page 134 Preliminary © 2007 Microchip Technology Inc. ...
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... TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY A simplified block diagram of the Timer1 module is shown in Figure 11-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 11-2. The module incorporates its own low-power oscillator to provide an additional clocking option ...
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... PIC18F85J90 FAMILY 11.1 Timer1 Operation Timer1 can operate in one of these modes: • Timer • Synchronous Counter • Asynchronous Counter The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). When TMR1CS is cleared (= 0), Timer1 increments on every internal instruction FIGURE 11-1: TIMER1 BLOCK DIAGRAM (8-BIT MODE) ...
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... T1OSI XTAL 32.768 kHz T1OSO Note: See the Notes with Table 11-1 for additional information about capacitor selection. © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY TABLE 11-1: CAPACITOR SELECTION FOR THE TIMER1 OSCILLATOR Oscillator Freq. Type LP 32.768 kHz Note 1: Microchip suggests these values as a starting point in validating the oscillator circuit ...
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... PIC18F85J90 FAMILY 11.3.2 TIMER1 OSCILLATOR LAYOUT CONSIDERATIONS The Timer1 oscillator circuit draws very little power during operation. Due to the low-power nature of the oscillator, it may also be sensitive to rapidly changing signals in close proximity. The oscillator circuit, shown in Figure 11-3, should be located as close as possible to the microcontroller. ...
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... T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC Legend: Shaded cells are not used by the Timer1 module. © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY ; Preload TMR1 register pair ; for 1 second overflow ; Configure for external clock, ; Asynchronous operation, external oscillator ; Initialize timekeeping registers ...
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... PIC18F85J90 FAMILY NOTES: DS39770B-page 140 Preliminary © 2007 Microchip Technology Inc. ...
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... Timer2 is off bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY 12.1 Timer2 Operation In normal operation, TMR2 is incremented from 00h on each clock (F /4). A 4-bit counter/prescaler on the OSC clock input gives direct input, divide-by-4 and divide-by-16 prescale options ...
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... PIC18F85J90 FAMILY 12.2 Timer2 Interrupt Timer2 can also generate an optional device interrupt. The Timer2 output signal (TMR2 to PR2 match) pro- vides the input for the 4-bit output counter/postscaler. This counter generates the TMR2 match interrupt flag which is latched in TMR2IF (PIR1<1>). The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE (PIE1< ...
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... TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY A simplified block diagram of the Timer3 module is shown in Figure 13-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 13-2. The Timer3 module is controlled through the T3CON register (Register 13-1) ...
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... PIC18F85J90 FAMILY 13.1 Timer3 Operation Timer3 can operate in one of three modes: • Timer • Synchronous Counter • Asynchronous Counter FIGURE 13-1: TIMER3 BLOCK DIAGRAM (8-BIT MODE) Timer1 Oscillator T1OSO/T13CKI T1OSI (1) T1OSCEN T3CKPS1:T3CKPS0 T3SYNC TMR3ON CCPx Special Event Trigger CCPx Select from T3CON<6,3> ...
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... T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module. © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY 13.4 Timer3 Interrupt The TMR3 register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and overflows to 0000h. The Timer3 interrupt, if enabled, is generated on overflow and is latched in interrupt flag bit, TMR3IF (PIR2< ...
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... PIC18F85J90 FAMILY NOTES: DS39770B-page 146 Preliminary © 2007 Microchip Technology Inc. ...
Page 149
... Note 1: CCPxM3:CCPxM0 = 1011 will only reset timer and not start A/D conversion on CCP1 match. © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY Each CCP module contains a 16-bit register which can operate as a 16-bit Capture register, a 16-bit Compare register or a PWM Master/Slave Duty Cycle register. ...
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... PIC18F85J90 FAMILY 14.1 CCP Module Configuration Each Capture/Compare/PWM module is associated with a control register (generically, CCPxCON) and a data register (CCPRx). The data register in turn is com- prised of two 8-bit registers: CCPRxL (low byte) and CCPRxH (high byte). All registers are both readable and writable. ...
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... Capture PWM None Compare PWM None PWM Capture None PWM Compare None PWM PWM Both PWMs will have the same frequency and update rate (TMR2 interrupt). © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY Interaction Preliminary DS39770B-page 149 ...
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... PIC18F85J90 FAMILY 14.2 Capture Mode In Capture mode, the CCPR2H:CCPR2L register pair captures the 16-bit value of the TMR1 or TMR3 register when an event occurs on the CCP2 pin (RC1 or RE7, depending on device configuration). An event is defined as one of the following: • every falling edge • every rising edge • ...
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... TMR3H TMR3L T3CCP1 Comparator CCPR2H CCPR2L © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY 14.3.3 SOFTWARE INTERRUPT MODE When the Generate Software Interrupt mode is chosen (CCP2M3:CCP2M0 = 1010), the CCP2 pin is not affected. Only a CCP interrupt is generated, if enabled, and the CCP2IE bit is set. ...
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... PIC18F85J90 FAMILY TABLE 14-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3 Name Bit 7 Bit 6 INTCON GIE/GIEH PEIE/GIEL TMR0IE RCON IPEN — PIR3 — LCDIF PIE3 — LCDIE IPR3 — LCDIP PIR2 OSCFIF CMIF PIE2 OSCFIE CMIE IPR2 OSCFIP CMIP TRISC ...
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... Q clock bits of the prescaler, to create the 10-bit time base. © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY A PWM output (Figure 14-5) has a time base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period) ...
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... PIC18F85J90 FAMILY 14.4.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPR2L register and to the CCP2CON<5:4> bits 10-bit resolution is available. The CCPR2L contains the eight MSbs and the CCP2CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR2L:CCP2CON<5:4>. The following equation is ...
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... Capture/Compare/PWM Register 2 High Byte CCP2CON — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM or Timer2. © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY 3. Make the CCP2 pin an output by clearing the appropriate TRIS bit. 4. Set the TMR2 prescale value, then enable Timer2 by writing to T2CON ...
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... PIC18F85J90 FAMILY NOTES: DS39770B-page 156 Preliminary © 2007 Microchip Technology Inc. ...
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... T13CKI Source Select INTRC Oscillator INTOSC Oscillator © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY The LCD driver module supports these features: • Direct driving of LCD panel • On-chip bias generator with dedicated charge pump to support a range of fixed and variable bias options • ...
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... PIC18F85J90 FAMILY 15.1 LCD Registers The LCD driver module has 33 registers: • LCD Control Register (LCDCON) • LCD Phase Register (LCDPS) • LCDREG Register (LCD Regulator Control) • Six LCD Segment Enable Registers (LCDSE5:LCDSE0) • 24 LCD Data Registers (LCDDATA23:LCDDATA0) 15.1.1 LCD CONTROL REGISTERS The LCDCON register, shown in Register 15-1, controls the overall operation of the module ...
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... Microchip Technology Inc. PIC18F85J90 FAMILY R-0 R/W-0 R/W-0 WA LP3 LP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 ...
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... PIC18F85J90 FAMILY REGISTER 15-3: LCDSEx: LCD SEGMENT ENABLE REGISTERS R/W-0 R/W-0 R/W bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 SEG(n + 7):SEG(n): Segment Enable bits For LCDSE0 For LCDSE1 For LCDSE2 For LCDSE3 For LCDSE4 ...
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... These registers are not implemented on 64-pin devices. © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY Individual LCDDATA bits are named by the convention “SxxCy”, with “xx” as the segment number and “y” as the common number. The relationship is summarized in Table 15-2. The prototype LCDDATA register is shown in Register 15-4 ...
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... PIC18F85J90 FAMILY 15.2 LCD Clock Source The LCD driver module generates its internal clock from 3 possible sources: • System clock (F /4) OSC • Timer1 oscillator • INTRC source The LCD clock generator uses a configurable divide-by-32/divide-by-8192 postscaler to produce a baseline frequency of about 1 kHz nominal, regardless of the source selected ...
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... DD on-chip LCD voltage regulator. 15.3.1 LCD BIAS TYPES PIC18F85J90 family devices support three bias types based on the waveforms generated to control segments and commons: • Static (two discrete levels) • 1/2 Bias (three discrete levels • 1/3 Bias (four discrete levels) The use of different waveforms in driving the LCD is dis- cussed in more detail in Section 15.8 “ ...
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... PIC18F85J90 FAMILY 15.3.3 BIAS CONFIGURATIONS PIC18F85J90 family devices have four distinct circuit configurations for LCD bias generation: • M0: Regulator with Boost • M1: Regulator without Boost • M2: Resistor Ladder with Software Contrast • M3: Resistor Ladder with Hardware Contrast 15.3.3.1 M0 (Regulator with Boost operation, the LCD charge pump feature is enabled ...
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... Note 1: These values are provided for design guidance only; they should be optimized for the application by the designer based on the actual LCD specifications. © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY configuration of the resistor ladder. Most applications using M2 will use a 1/3 or 1/2 Bias type. While Static ...
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... PIC18F85J90 FAMILY 15.3.3.4 M3 (Hardware Contrast) In M3, the LCD regulator is completely disabled. Like M2, LCD bias levels are tied and are generated DD using an external divider. The difference is that the inter- nal voltage reference is also disabled and the bottom of the ladder is tied to ground (V ); see Figure 15-5. The ...
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... LCDBIAS pins can be changed to increase or decrease current. As always, any changes should be evaluated in the actual circuit for its impact on the application. © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY 15.4 LCD Multiplex Types The LCD driver module can be configured into four multiplex types: • ...
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... PIC18F85J90 FAMILY 15.7 LCD Frame Frequency The rate at which the COM and SEG outputs changes is called the LCD frame frequency. Frame frequency is set by the LP3:LP0 bits (LCDPS<3:0>), and is also affected by the Multiplex mode being used. The rela- tionship between the Multiplex mode, LP bits setting and frame rate is shown in Table 15-4 and Table 15-5 ...
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... FIGURE 15-6: TYPE-A/TYPE-B WAVEFORMS IN STATIC DRIVE COM0 © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY COM0 SEG0 SEG1 COM0-SEG0 COM0-SEG1 1 Frame Preliminary DS39770B-page 169 ...
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... PIC18F85J90 FAMILY FIGURE 15-7: TYPE-A WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE COM1 COM0 COM0-SEG0 COM0-SEG1 DS39770B-page 170 COM0 COM1 SEG0 SEG1 1 Frame Preliminary © 2007 Microchip Technology Inc. ...
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... FIGURE 15-8: TYPE-B WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE COM1 COM0 COM0-SEG0 COM0-SEG1 © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY COM0 COM1 SEG0 SEG1 2 Frames Preliminary DS39770B-page 171 ...
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... PIC18F85J90 FAMILY FIGURE 15-9: TYPE-A WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE COM1 COM0 COM0-SEG0 COM0-SEG1 DS39770B-page 172 COM0 COM1 SEG0 SEG1 1 Frame Preliminary © 2007 Microchip Technology Inc. ...
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... FIGURE 15-10: TYPE-B WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE COM1 COM0 COM0-SEG0 COM0-SEG1 © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY COM0 COM1 SEG0 SEG1 2 Frames Preliminary DS39770B-page 173 ...
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... PIC18F85J90 FAMILY FIGURE 15-11: TYPE-A WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE COM2 COM1 COM0 COM0-SEG0 COM0-SEG1 DS39770B-page 174 COM0 COM1 COM2 SEG0 SEG2 SEG1 Preliminary Frame © 2007 Microchip Technology Inc. ...
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... FIGURE 15-12: TYPE-B WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE COM2 COM1 COM0 COM0-SEG0 COM0-SEG1 © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY COM0 COM1 COM2 SEG0 SEG1 Preliminary Frames DS39770B-page 175 ...
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... PIC18F85J90 FAMILY FIGURE 15-13: TYPE-A WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE COM2 COM1 COM0 DS39770B-page 176 COM0 COM1 COM2 SEG0 SEG2 SEG1 COM0-SEG0 COM0-SEG1 Preliminary Frame © 2007 Microchip Technology Inc. ...
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... FIGURE 15-14: TYPE-B WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE COM2 COM1 COM0 © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY COM0 COM1 COM2 SEG0 SEG1 COM0-SEG0 COM0-SEG1 Preliminary Frames DS39770B-page 177 ...
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... PIC18F85J90 FAMILY FIGURE 15-15: TYPE-A WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE COM3 COM2 COM1 COM0 COM0-SEG0 COM0-SEG1 DS39770B-page 178 COM0 COM1 COM2 COM3 SEG0 SEG1 1 Frame Preliminary © 2007 Microchip Technology Inc. ...
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... FIGURE 15-16: TYPE-B WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE COM3 COM2 COM1 COM0 COM0-SEG0 COM0-SEG1 © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY COM0 COM1 COM2 COM3 SEG0 SEG1 2 Frames Preliminary DS39770B-page 179 ...
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... PIC18F85J90 FAMILY 15.9 LCD Interrupts The LCD timing generation provides an interrupt that defines the LCD frame timing. This interrupt can be used to coordinate the writing of the pixel data with the start of a new frame. Writing pixel data at the frame boundary allows a visually crisp transition of the image. ...
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... COM2 SEG0 2 Frames SLEEP Instruction Execution © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY internal oscillators (either INTRC or INTOSC as the default system clock). While in Sleep, the LCD data cannot be changed. The LCD module current consumption will not decrease in this mode; however, the overall consumption of the device will be lower due to shut down of the core and other peripheral functions ...
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... PIC18F85J90 FAMILY 15.11 Configuring the LCD Module The following is the sequence of steps to configure the LCD module. 1. Select the frame clock prescale using bits LP3:LP0 (LCDPS<3:0>). 2. Configure the appropriate pins to function as segment drivers using the LCDSEx registers. 3. Configure the appropriate pins as inputs using TRISx registers ...
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... BIASMD LCDREG — CPEN Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for LCD operation. Note 1: These registers or individual bits are unimplemented on 64-pin devices. © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF ...
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... PIC18F85J90 FAMILY NOTES: DS39770B-page 184 Preliminary © 2007 Microchip Technology Inc. ...
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... MSSP module 2 is operated in SPI mode. Additional details are provided under the individual sections. © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY 16.3 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four modes of ...
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... PIC18F85J90 FAMILY 16.3.1 REGISTERS Each MSSP module has four registers for SPI mode operation. These are: • MSSP Control Register 1 (SSPCON1) • MSSP Status Register (SSPSTAT) • Serial Receive/Transmit Buffer Register (SSPBUF) • MSSP Shift Register (SSPSR) – Not directly accessible SSPCON1 and SSPSTAT are the control and status registers in SPI mode operation ...
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... In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 2: When enabled, these pins must be properly configured as input or output. 3: Bit combinations not specifically listed here are either reserved or implemented in I © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY R/W-0 R/W-0 (2) (3) CKP SSPM3 SSPM2 U = Unimplemented bit, read as ‘ ...
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... PIC18F85J90 FAMILY 16.3.2 OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPCON1<5:0> and SSPSTAT<7:6>). These control bits allow the following to be specified: • Master mode (SCK is the clock output) • Slave mode (SCK is the clock input) • ...
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... MSb LSb PROCESSOR 1 © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY to a higher level through an external pull-up resistor, and allows the output to communicate with external circuits without the need for additional level shifters. The open-drain output option is controlled by the SPIOD bit (TRISG<7>). Setting the bit configures both pins for open-drain operation ...
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... PIC18F85J90 FAMILY 16.3.6 MASTER MODE The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 2, Figure 16-2) will broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI is only going to receive, the SDO output could be dis- abled (programmed as an input) ...
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... SSPIF Interrupt Flag SSPSR to SSPBUF © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY driven. When the SS pin goes high, the SDO pin is no longer driven, even if in the middle of a transmitted byte and becomes pull-up/pull-down resistors may be desirable depending on the application. ...
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... PIC18F85J90 FAMILY FIGURE 16-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit 7 SDI (SMP = 0) bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF FIGURE 16-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) ...
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... SMP CKE Legend: Shaded cells are not used by the MSSP module in SPI mode. © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY mode and Transmit/Receive Shift register. When all 8 bits have been received, the MSSP interrupt flag bit will be set and if enabled, will wake the device. ...
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... PIC18F85J90 FAMILY 2 16 Mode 2 The MSSP module mode fully implements all master and slave functions (including general call support) and provides interrupts on Start and Stop bits in hardware to determine a free bus (multi-master function). The MSSP module implements the standard mode specifications as well as 7-bit and 10-bit addressing ...
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... This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit or not ACK bit. 3: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Active mode. © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY 2 C™ MODE) R-0 R-0 ...
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... PIC18F85J90 FAMILY REGISTER 16-4: SSPCON1: MSSP CONTROL REGISTER 1 (I R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 WCOL: Write Collision Detect bit In Master Transmit mode write to the SSPBUF register was attempted while the I ...
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... Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive the I C module is active, these bits may not be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled). © 2007 Microchip Technology Inc. PIC18F85J90 FAMILY 2 C™ MASTER MODE) R/W-0 R/W-0 (1) (2) ...
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... PIC18F85J90 FAMILY REGISTER 16-6: SSPCON2: MSSP CONTROL REGISTER 2 (I R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ADMSK5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 GCEN: General Call Enable bit 1 = Enable interrupt when a general call address (0000h) is received in the SSPSR ...