ATMEGA32U2-AU Atmel, ATMEGA32U2-AU Datasheet - Page 293
ATMEGA32U2-AU
Manufacturer Part Number
ATMEGA32U2-AU
Description
IC MCU 8BIT 32KB FLASH 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA32U2-AU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
Processor Series
ATMEGA32x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPI, UART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
22
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525
Minimum Operating Temperature
- 40 C
Controller Family/series
AVR MEGA
No. Of I/o's
22
Eeprom Memory Size
1KB
Ram Memory Size
1KB
Cpu Speed
16MHz
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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- Download datasheet (6Mb)
7799D–AVR–11/10
Mnemonics
BREAK
MOVW
SLEEP
SWAP
BSET
BCLR
PUSH
ROR
MOV
WDR
ROL
ASR
SEC
CLC
SEN
CLN
SES
SEV
SEH
CLH
LDD
LDD
STD
STD
LPM
LPM
LPM
SPM
OUT
POP
NOP
BST
BLD
SEZ
CLZ
CLS
CLV
SET
CLT
LDS
STS
SEI
CLI
LDI
LD
LD
LD
LD
LD
LD
LD
LD
LD
ST
ST
ST
ST
ST
ST
ST
ST
ST
IN
Operands
Rd, Z+q
Rd,Y+q
Rd, X+
Rd, - X
Rd, Y+
Rd, - Y
Rd, Z+
Y+q,Rr
Z+q,Rr
Rd, Z+
Rd, Rr
Rd, Rr
X+, Rr
- X, Rr
Y+, Rr
- Y, Rr
Rd, -Z
Z+, Rr
Rd, K
Rd, X
Rd, Y
Rd, Z
-Z, Rr
Rd, Z
Rd, P
Rd, b
Rd, k
X, Rr
Y, Rr
P, Rr
Rr, b
Z, Rr
k, Rr
Rd
Rd
Rd
Rd
Rd
Rr
s
s
DATA TRANSFER INSTRUCTIONS
MCU CONTROL INSTRUCTIONS
Load Program Memory and Post-Inc
Clear Twos Complement Overflow
Set Twos Complement Overflow.
Store Indirect with Displacement
Store Indirect with Displacement
Load Indirect with Displacement
Load Indirect with Displacement
Clear Half Carry Flag in SREG
Set Half Carry Flag in SREG
Rotate Right Through Carry
Bit Store from Register to T
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Rotate Left Through Carry
Bit load from T to Register
Move Between Registers
Pop Register from Stack
Load Direct from SRAM
Global Interrupt Disable
Store Program Memory
Push Register on Stack
Global Interrupt Enable
Clear Signed Test Flag
Load Program Memory
Load Program Memory
Store Direct to SRAM
Arithmetic Shift Right
Set Signed Test Flag
Copy Register Word
Clear Negative Flag
Set Negative Flag
Clear T in SREG
Watchdog Reset
Load Immediate
Clear Zero Flag
Set T in SREG
Description
Swap Nibbles
Set Zero Flag
Store Indirect
No Operation
Load Indirect
Load Indirect
Load Indirect
Store Indirect
Store Indirect
Clear Carry
Flag Clear
Set Carry
Flag Set
Out Port
In Port
Break
Sleep
(see specific descr. for Sleep function)
Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)
Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)
Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)
(see specific descr. for WDR/timer)
Rd(n) ← Rd(n+1), n=0..6
ATmega8U2/16U2/32U2
For On-chip Debug Only
Rd ← (X), X ← X + 1
Rd ← (Y), Y ← Y + 1
Rd+1:Rd ← Rr+1:Rr
X ← X - 1, Rd ← (X)
Y ← Y - 1, Rd ← (Y)
Z ← Z - 1, Rd ← (Z)
(X) ← Rr, X ← X + 1
(Y) ← Rr, Y ← Y + 1
(Z) ← Rr, Z ← Z + 1
X ← X - 1, (X) ← Rr
Y ← Y - 1, (Y) ← Rr
Rd ← (Z), Z ← Z+1
Z ← Z - 1, (Z) ← Rr
Rd ← (Z), Z ← Z+1
SREG(s) ← 1
SREG(s) ← 0
Rd ← STACK
STACK ← Rr
Rd ← (Y + q)
Rd ← (Z + q)
(Y + q) ← Rr
(Z + q) ← Rr
(Z) ← R1:R0
Operation
Rd(b) ← T
T ← Rr(b)
Rd ← (X)
Rd ← (Y)
Rd ← (k)
Rd ← (Z)
R0 ← (Z)
Rd ← (Z)
Rd ← Rr
Rd ← K
(X) ← Rr
(Y) ← Rr
(Z) ← Rr
(k) ← Rr
Rd ← P
P ← Rr
C ← 1
C ← 0
N ← 1
N ← 0
S ← 1
S ← 0
V ← 1
V ← 0
H ← 1
H ← 0
Z ← 1
Z ← 0
T ← 1
T ← 0
I ← 1
I ← 0
SREG(s)
SREG(s)
Z,C,N,V
Z,C,N,V
Z,C,N,V
Flags
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
C
C
N
N
H
H
T
Z
Z
S
S
V
V
T
T
I
I
#Clocks
N/A
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
1
1
2
2
1
1
1
-
293
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