AT32UC3B164-Z1UR Atmel, AT32UC3B164-Z1UR Datasheet - Page 26
![MCU AVR32 64K FLASH 48-QFN](/photos/6/82/68297/48-qfn_sml.jpg)
AT32UC3B164-Z1UR
Manufacturer Part Number
AT32UC3B164-Z1UR
Description
MCU AVR32 64K FLASH 48-QFN
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet
1.AT32UC3B164-Z1UT.pdf
(105 pages)
Specifications of AT32UC3B164-Z1UR
Core Processor
AVR
Core Size
32-Bit
Speed
60MHz
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
28
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN Exposed Pad
For Use With
ATSTK600-TQFP48 - STK600 SOCKET/ADAPTER 48-TQFPATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1101 - KIT DEV/EVAL FOR AVR32 AT32UC3B
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
6.5
6.5.1
32059K–03/2011
Exceptions and Interrupts
System Stack Issues
Table 6-3.
AVR32UC incorporates a powerful exception handling scheme. The different exception sources,
like Illegal Op-code and external interrupt requests, have different priority levels, ensuring a well-
defined behavior when multiple exceptions are received simultaneously. Additionally, pending
exceptions of a higher priority class may preempt handling of ongoing exceptions of a lower pri-
ority class.
When an event occurs, the execution of the instruction stream is halted, and execution control is
passed to an event handler at an address specified in
dlers are placed sequentially in the code space starting at the address specified by EVBA, with
four bytes between each handler. This gives ample space for a jump instruction to be placed
there, jumping to the event routine itself. A few critical handlers have larger spacing between
them, allowing the entire event routine to be placed directly at the address specified by the
EVBA-relative offset generated by hardware. All external interrupt sources have autovectored
interrupt service routine (ISR) addresses. This allows the interrupt controller to directly specify
the ISR address as an address relative to EVBA. The autovector offset has 14 address bits, giv-
ing an offset of maximum 16384 bytes. The target address of the event handler is calculated as
(EVBA | event_handler_offset), not (EVBA + event_handler_offset), so EVBA and exception
code segments must be set up appropriately. The same mechanisms are used to service all dif-
ferent types of events, including external interrupt requests, yielding a uniform event handling
scheme.
An interrupt controller does the priority handling of the external interrupts and provides the
autovector offset to the CPU.
Event handling in AVR32UC uses the system stack pointed to by the system stack pointer,
SP_SYS, for pushing and popping R8-R12, LR, status register, and return address. Since event
code may be timing-critical, SP_SYS should point to memory addresses in the IRAM section,
since the timing of accesses to this memory section is both fast and deterministic.
Reg #
92
93
94
95
96
97
98
99
100
101
102
103-191
192-255
Address
368
372
376
380
384
388
392
396
400
404
408
448-764
768-1020
System Registers (Continued)
Name
MPUPSR4
MPUPSR5
MPUPSR6
MPUPSR7
MPUCRA
MPUCRB
MPUBRA
MPUBRB
MPUAPRA
MPUAPRB
MPUCR
Reserved
IMPL
Function
MPU Privilege Select Register region 4
MPU Privilege Select Register region 5
MPU Privilege Select Register region 6
MPU Privilege Select Register region 7
Unused in this version of AVR32UC
Unused in this version of AVR32UC
Unused in this version of AVR32UC
Unused in this version of AVR32UC
MPU Access Permission Register A
MPU Access Permission Register B
MPU Control Register
Reserved for future use
IMPLEMENTATION DEFINED
Table 6-4 on page
AT32UC3B
29. Most of the han-
26