PIC18LF27J53-I/SO Microchip Technology, PIC18LF27J53-I/SO Datasheet - Page 228
PIC18LF27J53-I/SO
Manufacturer Part Number
PIC18LF27J53-I/SO
Description
IC PIC MCU 128KB FLASH 28SOIC
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF24J10-ISS.pdf
(32 pages)
2.PIC18F26J13-ISS.pdf
(496 pages)
3.PIC18F26J53-ISS.pdf
(586 pages)
4.PIC18F26J53-ISS.pdf
(12 pages)
Specifications of PIC18LF27J53-I/SO
Core Size
8-Bit
Program Memory Size
128KB (64K x 16)
Core Processor
PIC
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 2.75 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Controller Family/series
PIC18
Cpu Speed
48MHz
Digital Ic Case Style
SOIC
Supply Voltage Range
1.8V To 3.6V
Embedded Interface Type
I2C, SPI, USART
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
- PIC18LF24J10-ISS PDF datasheet
- PIC18F26J13-ISS PDF datasheet #2
- PIC18F26J53-ISS PDF datasheet #3
- PIC18F26J53-ISS PDF datasheet #4
- Current page: 228 of 586
- Download datasheet (6Mb)
PIC18F47J53 FAMILY
15.5.4
When Timer3/5 Gate Single Pulse mode is enabled, it
is possible to capture a single pulse gate event.
Timer3/5 Gate Single Pulse mode is first enabled by
setting the TxGSPM bit (TxGCON<4>). Next, the
TxGGO/TxDONE bit (TxGCON<3>) must be set.
The Timer3/5 will be fully enabled on the next incre-
menting edge. On the next trailing edge of the pulse,
the TxGGO/TxDONE bit will automatically be cleared.
FIGURE 15-4:
DS39964B-page 228
TMRxGIF
TMRxGE
TxGSPM
TxDONE
TxGPOL
Timer3/5
TxGGO/
TxGVAL
TxG_IN
TxCKI
TIMER3/5 GATE SINGLE PULSE
MODE
TIMER3/5 GATE SINGLE PULSE MODE
N
Cleared by Software
Counting Enabled on
Rising Edge of TxG
Set by Software
Preliminary
N + 1
No other gate events will be allowed to increment
Timer3/5 until the TxGGO/TxDONE bit is once again
set in software.
Clearing the TxGSPM bit will also clear the
TxGGO/TxDONE
Figure 15-4.)
Simultaneously, enabling the Toggle mode and the
Single Pulse mode will permit both sections to work
together. This allows the cycle times on the Timer3/5
gate source to be measured. (For timing details, see
Figure 15-5.)
Set by Hardware on
Falling Edge of TxGVAL
Cleared by Hardware on
Falling Edge of TxGVAL
N + 2
bit.
2010 Microchip Technology Inc.
(For
timing
Software
Cleared by
details,
see
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