ATMEGA164A-PU Atmel, ATMEGA164A-PU Datasheet - Page 194

IC MCU AVR 16K 20MHZ 40PDIP

ATMEGA164A-PU

Manufacturer Part Number
ATMEGA164A-PU
Description
IC MCU AVR 16K 20MHZ 40PDIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA164A-PU

Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Controller Family/series
Atmega
No. Of I/o's
32
Eeprom Memory Size
512Byte
Ram Memory Size
1KB
Cpu Speed
20MHz
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA164A-PU
Manufacturer:
ATMEL
Quantity:
300
18.11.5
8272A–AVR–01/10
UBRRnL and UBRRnH – USART Baud Rate Registers
• Bit 0 – UCPOLn: Clock Polarity
This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is
used. The UCPOLn bit sets the relationship between data output change and data input sample,
and the synchronous clock (XCKn).
Table 18-8.
• Bit 15:12 – Reserved Bits
These bits are reserved for future use. For compatibility with future devices, these bit must be
written to zero when UBRRH is written.
• Bit 11:0 – UBRR11:0: USART Baud Rate Register
This is a 12-bit register which contains the USART baud rate. The UBRRH contains the four
most significant bits, and the UBRRL contains the eight least significant bits of the USART baud
rate. Ongoing transmissions by the Transmitter and Receiver will be corrupted if the baud rate is
changed. Writing UBRRL will trigger an immediate update of the baud rate prescaler.
164A/164PA/324A/324PA/644A/644PA/1284/1284P
Bit
Read/Write
Initial Value
UCPOLn
0
1
UCPOLn Bit Settings
Transmitted Data Changed (Output of
TxDn Pin)
Rising XCKn Edge
Falling XCKn Edge
R/W
15
R
7
0
0
R/W
14
R
6
0
0
R/W
13
R
5
0
0
R/W
12
R
4
0
0
UBRR[7:0]
R/W
R/W
11
3
0
0
Falling XCKn Edge
Received Data Sampled (Input on RxDn
Pin)
Rising XCKn Edge
R/W
R/W
10
2
0
0
UBRR[11:8]
R/W
R/W
9
1
0
0
R/W
R/W
8
0
0
0
UBRRHn
UBRRLn
194

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