DSPIC30F4013-20E/PT Microchip Technology, DSPIC30F4013-20E/PT Datasheet

DSPIC30F4013-20E/PT

Manufacturer Part Number

DSPIC30F4013-20E/PT

Description

IC DSPIC MCU/DSP 48K 44TQFP

Manufacturer

Microchip Technology

Series

dsPIC™ 30Fr

Datasheets

1.DSPIC30F2011-20ISO.pdf (66 pages)

2.DSPIC30F3014-30IPT.pdf (228 pages)

3.DSPIC30F3014-30IPT.pdf (16 pages)

4.DSPIC30F3014-30IPT.pdf (6 pages)

5.DSPIC30F3014-30IPT.pdf (14 pages)

6.DSPIC30F3014-30IPT.pdf (20 pages)

7.DSPIC30F4013-20EPT.pdf (220 pages)

8.DSPIC30F3014-20IP.pdf (226 pages)

Specifications of DSPIC30F4013-20E/PT

Program Memory Type

FLASH

Program Memory Size

48KB (16K x 24)

Package / Case

44-TQFP, 44-VQFP

Core Processor

dsPIC

Core Size

16-Bit

Speed

20 MIPS

Connectivity

CAN, I²C, SPI, UART/USART

Peripherals

AC'97, Brown-out Detect/Reset, I²S, POR, PWM, WDT

Number Of I /o

Eeprom Size

1K x 8

Ram Size

2K x 8

Voltage - Supply (vcc/vdd)

2.5 V ~ 5.5 V

Data Converters

A/D 13x12b

Oscillator Type

Internal

Operating Temperature

-40°C ~ 125°C

Product

DSCs

Data Bus Width

16 bit

Processor Series

DSPIC30F

Core

dsPIC

Maximum Clock Frequency

20 MHz

Number Of Programmable I/os

Data Ram Size

2 KB

Maximum Operating Temperature

+ 125 C

Mounting Style

SMD/SMT

3rd Party Development Tools

52713-733, 52714-737, 53276-922, EWDSPIC

Development Tools By Supplier

PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011

Minimum Operating Temperature

- 40 C

Package

44TQFP

Device Core

dsPIC

Family Name

dsPIC30

Maximum Speed

20 MHz

Operating Supply Voltage

3.3|5 V

Interface Type

CAN/I2C/SPI/UART

On-chip Adc

13-chx12-bit

Number Of Timers

Core Frequency

20MHz

Embedded Interface Type

CAN, I2C, SPI, UART

No. Of I/o's

Flash Memory Size

48KB

Supply Voltage Range

2.5V To 5.5V

Rohs Compliant

Yes

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

For Use With

AC30F006 - MODULE SKT FOR DSPIC30F 44TQFP

Lead Free Status / Rohs Status

Lead free / RoHS Compliant

Other names

DSPIC30F401320EPT

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

BOSTOCK HK LIMITED

Part Number:

DSPIC30F4013-20E/PT

Manufacturer:

Microchip Technology

Quantity:

10 000

Current page: 1 of 14
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The dsPIC30F3014/4013 (Rev. A2) samples that you

have received were found to conform to the

specifications and functionality described in the

following documents:

• DS70157 – “dsPIC30F/33F Programmer’s

• DS70138 – “dsPIC30F3014/4013 Data Sheet”

• DS70046 – “dsPIC30F Family Reference Manual”

The exceptions to the specifications in the documents

listed above are described in this section. These

exceptions are described for the specific devices listed

below:

• dsPIC30F3014

• dsPIC30F4013

These devices may be identified by the following

message that appears in the MPLAB

Window under MPLAB IDE, when a “Reset and

Connect” operation is performed within MPLAB IDE:

Setting Vdd source to target

Target Device dsPIC30F4013 found,

revision = 0x1002

...Reading ICD Product ID

Running ICD Self Test

...Passed

MPLAB ICD 2 Ready

The errata described in this section will be addressed

dsPIC30F4013 devices.

Silicon Errata Summary

The following list summarizes the errata described in

this document:

Reference Manual”

MAC Class Instructions with ±4 Address

Modification

Sequential MAC instructions, which prefetch data

from Y data space using ±4 address modification,

will cause an address error trap.

Decimal Adjust Instruction

The Decimal Adjust instruction, DAW.b, may

improperly clear the Carry bit, C (SR<0>).

PSV Operations Using SR

In certain instructions, fetching one of the

operands from program memory using Program

Space Visibility (PSV) will corrupt specific bits in

the STATUS Register, SR.

future

revisions

dsPIC30F3014/4013 Rev. A2 Silicon Errata

dsPIC30F3014

ICD 2 Output

dsPIC30F3014/4013

and

10. Output Compare

11. Special Function Registers

12. 4x PLL Operation

13. The data pin (SDA) on the I

14. INT0, ADC and Sleep Mode

Sequential Interrupts

Sequential interrupts after modifying the CPU IPL,

interrupt IPL, interrupt enable or interrupt flag may

cause an address error trap.

DISI Instruction

The DISI instruction will not disable interrupts if a

DISI instruction is executed in the same

instruction

decrements to zero.

Early Termination of Nested DO Loops

When using two DO loops in a nested fashion,

terminating the inner-level DO loop by setting the

EDT (CORCON<11>) bit will produce unexpected

results.

32 kHz Low-Power (LP) Oscillator

The LP oscillator does not function when the

device is placed in Sleep mode.

Data Converter Interface (DCI)

Once enabled, if the DCI module is subsequently

disabled by the application, the module does not

release the ownership of the COFS, CSCK, CSDI

and CSDO pins to the associated port functions

(RB9, RB10, RB11 and RB12).

Output Compare Module in PWM Mode

Output compare will produce a glitch when

loading 0% duty cycle in PWM mode. It will also

miss the next compare after the glitch.

The output compare module will produce a glitch

on the output when an I/O pin is initially set high

and the module is configured to drive the pin low at

a specified time.

Writes to certain unimplemented address locations

can affect I/O Port register values.

The 4x PLL mode of operation may not function

correctly for certain input frequencies.

not function unless the LATF<2> bit is low.

ADC event triggers from the INT0 pin will not

wake-up the device from Sleep mode if the SMPI

bits are non-zero.

cycle

that

the

C™ module does

DS80397A-page 1

DISI

counter

Related parts for DSPIC30F4013-20E/PT

DSPIC30F4013-20E/PT Summary of contents

Page 1

... These devices may be identified by the following message that appears in the MPLAB Window under MPLAB IDE, when a “Reset and Connect” operation is performed within MPLAB IDE: Setting Vdd source to target Target Device dsPIC30F4013 found, revision = 0x1002 ...Reading ICD Product ID Running ICD Self Test ...Passed ...

Page 2

... SDA and SCL pins, causing a false communication start in a single-master configuration or a bus collision in a multi-master configuration. The following sections describe the errata and work around to these errata, where they may apply. © 2008 Microchip Technology Inc. ® DSC ...

Page 3

... Adding an accumulator write back (a dummy write back if needed) to either of the MAC class instructions not use the + = address modification not prefetch data from Y data space. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 2. Module: CPU – Instruction DAW.b The Decimal Adjust instruction, DAW.b, may improperly clear the Carry bit, C (SR< ...

Page 4

... Result in W4 (3) SR<1:0> bits , Result in W2 (3) SR<1:0> bits (4) SR<15:10> bits CORRECT RESULTS ;Load PSVPAG register ;Enable PSV ;Set up W1 for ;indirect PSV access ;from 0x000200 ;works ok ;Load W2 with data ;from program memory ;Carry flag and W4 ;results are ok! © 2008 Microchip Technology Inc. ...

Page 5

... DISI_PROTECT(X) {\ __asm__ volatile (“DISI #0x1FFF”);\ X; \ DISICNT = 0; } DISI_PROTECT(SRbits.IPL = 0x5); © 2008 Microchip Technology Inc. dsPIC30F3014/4013 Work around The user may disable interrupt nesting or execute a DISI instruction before modifying the CPU IPL or Interrupt 1 setting. A minimum DISI value required if the DISI is executed immediately before the CPU IPL or Interrupt 1 is modified, as shown in Example 4 ...

Page 6

... After disabling the DCI module by clearing the DCIEN bit, the application should further set the DCI Module Disable bit, DCIMD (PMD1<8>). The port functions associated with the DCI module (RB9, RB10, RB11 and RB12) may now be used. © 2008 Microchip Technology Inc. ...

Page 7

... PORTE will be modified by a write to address 0x0DA PORTF will be modified by a write to address 0x0E0 Work around User software should avoid writing to the unimplemented locations listed above. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 12. Module: 4x PLL Operation When the 4x PLL mode of operation is selected, . ...

Page 8

... For applications using the C language, MPLAB C30 version 3.11 or higher, provides the following command-line switch that implements a work around for the erratum. -merrata=psv_trap Refer to the readme.txt file in the MPLAB C30 v3.11 tool suite for further details. © 2008 Microchip Technology Inc. ...

Page 9

... This will also clear the RBF flag Clear the I C receiver interrupt flag SI2CF back to step 1 to continue receiving incoming data bytes. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 Work around 2: Use this work around for applications in which the receiver interrupt is required. Assuming that ...

Page 10

... C bus, and can cause 2 C module are set to values ‘1’ and 2 C module and the first data 2 C masters should be synchro module to be initialized 2 C module is with other modules that have 2 C module module. © 2008 Microchip Technology Inc. ...

Page 11

Page 12

Page 13

... PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

Page 14

... Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2008 Microchip Technology Inc. 01/02/08 ...

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