DSPIC30F4013-20E/PT Microchip Technology, DSPIC30F4013-20E/PT Datasheet
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... Microchip Technology Inc. dsPIC30F3014/4013 Data Sheet High-Performance, 16-Bit Digital Signal Controllers DS70138F ...
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... PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Single-Cycle Hardware Fractional/Integer Multiplier • All DSP Instructions are Single Cycle - Multiply-Accumulate (MAC) Operation • Single-Cycle ±16 Shift © 2008 Microchip Technology Inc. dsPIC30F3014/4013 Peripheral Features: • High-Current Sink/Source I/O Pins: 25 mA/25 mA • Five 16-Bit Timers/Counters; Optionally Pair ...
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... Wide Operating Voltage Range (2.5V to 5.5V) • Industrial and Extended Temperature Ranges • Low-Power Consumption dsPIC30F3014/4013 Controller Family Program Memory Device Pins Bytes Instructions dsPIC30F3014 40/44 24K 8K dsPIC30F4013 40/44 48K 16K DS70138F-page 2 Output SRAM EEPROM Timer Input Comp/ Bytes Bytes ...
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... Pin Diagrams 40-Pin PDIP AN0/V AN1/V AN2/SS1/LVDIN/CN4/RB2 PGC/EMUC/AN6/OCFA/RB6 PGD/EMUD/AN7/RB7 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 © 2008 Microchip Technology Inc. dsPIC30F3014/4013 AV MCLR 1 40 +/CN2/RB0 AVss REF 2 39 -/CN3/RB1 AN9/RB9 REF 3 38 AN10/RB10 4 37 AN3/CN5/RB3 AN11/RB11 5 36 AN4/CN6/RB4 AN12/RB12 6 35 AN5/CN7/RB5 EMUC2/OC1/RD0 7 34 EMUD2/OC2/RD1 AN8/RB8 10 31 ...
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... TQFP U1RX/SDI1/SDA/RF2 U2TX/CN18/RF5 U2RX/CN17/RF4 RF1 RF0 EMUD2/OC2/RD1 EMUC2/OC1/RD0 AN12/RB12 AN11/RB11 Note 1: For descriptions of individual pins, see Section 1.0 “Device Overview”. DS70138F-page EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 32 2 OSC2/CLKO/RC15 31 3 OSC1/CLKI dsPIC30F3014 AN8/RB8 27 7 PGD/EMUD/AN7/RB7 26 8 PGC/EMUC/AN6/OCFA/RB6 9 25 AN5/CN7/RB5 AN4/CN6/RB4 11 © 2008 Microchip Technology Inc. ...
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... Pin Diagrams (Continued) 44-Pin QFN U1RX/SDI1/SDA/RF2 1 U2TX/CN18/RF5 2 U2RX/CN17/RF4 3 RF1 4 RF0 EMUD2/OC2/RD1 9 EMUC2/OC1/RD0 10 AN12/RB12 11 Note 1: For descriptions of individual pins, see Section 1.0 “Device Overview”. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 OSC2/CLKO/RC15 33 OSC1/CLKI dsPIC30F3014 DD 28 AN8/RB8 27 PGD/EMUD/AN7/RB7 26 PGC/EMUC/AN6/OCFA/RB6 25 AN5/CN7/RB5 24 AN4/CN6/RB4 23 DS70138F-page 5 ...
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... DD AN8/RB8 C1RX/RF0 C1TX/RF1 U2RX/CN17/RF4 OSC1/CLKI 13 U2TX/CN18/RF5 OSC2/CLKO/RC15 14 27 U1RX/SDI1/SDA/RF2 15 26 EMUD3/U1TX/SDO1/SCL/RF3 16 25 EMUC3/SCK1/RF6 17 24 INT0/RA11 IC1/INT1/RD8 18 23 IC2/INT2/RD9 OC3/RD2 19 22 OC4/RD3 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 32 2 OSC2/CLKO/RC15 31 3 OSC1/CLKI dsPIC30F4013 AN8/RB8 27 7 PGD/EMUD/AN7/RB7 26 8 PGC/EMUC/AN6/OCFA/RB6 9 25 AN5/IC8/CN7/RB5 AN4/IC7/CN6/RB4 © 2008 Microchip Technology Inc. ...
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... Pin Diagrams (Continued) 44-Pin QFN U1RX/SDI1/SDA/RF2 U2TX/CN18/RF5 U2RX/CN17/RF4 C1TX/RF1 C1RX/RF0 EMUD2/OC2/RD1 10 EMUC2/OC1/RD0 AN12/COFS/RB12 11 Note 1: For descriptions of individual pins, see Section 1.0 “Device Overview”. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 1 33 OSC2/CLKO/RC15 2 32 OSC1/CLKI dsPIC30F4013 AN8/RB8 PGD/EMUD/AN7/RB7 8 26 PGC/EMUC/AN6/OCFA/RB6 9 25 AN5/IC8/CN7/RB5 24 AN4/IC7/CN6/RB4 23 DS70138F-page 7 ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS70138F-page 8 © 2008 Microchip Technology Inc. ...
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... This document contains specific information for the dsPIC30F3014/4013 Digital Signal Controller (DSC) devices. The dsPIC30F3014/4013 devices contain extensive Digital Signal Processor (DSP) functionality within a high-performance, 16-bit microcontroller (MCU) architecture. Figure 1-1 and Figure 1-2 show device block diagrams for dsPIC30F3014 and dsPIC30F4013, respectively. X Data Bus Data Latch ...
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... FIGURE 1-2: dsPIC30F4013 BLOCK DIAGRAM Y Data Bus Interrupt PSV & Table Controller Data Access 8 24 Control Block 24 24 PCU Program Counter Stack Address Latch Control Logic Program Memory (48 Kbytes) Data EEPROM (1 Kbyte) 16 Data Latch ROM Latch 24 16 Instruction Decode & ...
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... PGC I Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input © 2008 Microchip Technology Inc. dsPIC30F3014/4013 Buffer Description Type Analog Analog input channels. AN6 and AN7 are also used for device programming data and clock inputs, respectively. ...
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... Positive supply for logic and I/O pins. — Ground reference for logic and I/O pins. Analog Analog voltage reference (high) input. Analog Analog voltage reference (low) input. Analog = Analog input O = Output P = Power Description 2 C™ © 2008 Microchip Technology Inc. ...
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... Each data word consists of 2 bytes, and most instructions can address data either as words or bytes. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 There are two methods of accessing data stored in program memory: • The upper 32 Kbytes of data space memory can ...
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... The upper byte of the STATUS register contains the DSP adder/subtracter Status bits, the DO Loop Active bit (DA) and the Digit Carry (DC) Status bit. 2.2.3 PROGRAM COUNTER The program counter is 23 bits wide; bit 0 is always clear. Therefore, the PC can address instruction words. © 2008 Microchip Technology Inc. ...
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... AD39 AccA DSP Accumulators AccB PC22 0 7 TABPAG TBLPAG Data Table Page Address 7 0 PSVPAG PSVPAG OAB SAB DA SRH © 2008 Microchip Technology Inc. dsPIC30F3014/4013 D15 D0 W0/WREG W10 W11 W12/DSP Offset W13/DSP Write-Back W14/Frame Pointer W15/Stack Pointer SPLIM AD31 AD15 PC0 ...
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... The REPEAT loop count must be setup for 18 iterations of the DIV/DIVF instruction. Thus, a complete divide operation requires 19 cycles. Note: The divide flow is interruptible. However, the user needs to save the context as appropriate. Function © 2008 Microchip Technology Inc. ...
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... ED EDAC MAC MAC MOVSAC MPY MPY.N MSC © 2008 Microchip Technology Inc. dsPIC30F3014/4013 The DSP engine has various options selected through various bits in the CPU Core Configuration register (CORCON), as listed below: 1. Fractional or integer DSP multiply (IF). 2. Signed or unsigned DSP multiply (US). ...
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... FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In DS70138F-page 18 40-Bit Accumulator A 40-Bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-Bit Multiplier/Scaler 16 16 To/From W Array Round u Logic Zero Backfill © 2008 Microchip Technology Inc. ...
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... For the ADD and LAC instructions, the data to be accumulated or loaded can be optionally scaled via the barrel shifter prior to accumulation. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 2.4.2.1 Adder/Subtracter, Overflow and Saturation The adder/subtracter is a 40-bit adder with an optional zero input into one side and either true or complement data into the other input ...
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... Space Write Saturation”). Note that for the MAC class of instructions, the accumulator write-back operation functions in the same manner, addressing combined MCU (X and Y) data space though the X bus. For this class of instructions, the data is always subject to rounding. © 2008 Microchip Technology Inc. ...
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... If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 2.4.3 BARREL SHIFTER The barrel shifter is capable of performing up to 16-bit arithmetic or logic right shifts 16-bit left shifts in a single cycle ...
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... NOTES: DS70138F-page 22 © 2008 Microchip Technology Inc. ...
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... F7FFFE F80000 F8000E F80010 FEFFFE FF0000 FF0002 dsPIC30F4013 PROGRAM SPACE MEMORY MAP Reset – GOTO Instruction 000000 Reset – Target Address 000002 000004 Interrupt Vector Table 00007E 000080 Reserved 000084 Alternate Vector Table 0000FE ...
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... Program space visibility cannot be used to access bits<23:16> word in program memory. DS70138F-page 24 Program Space Address <23> <22:16> 0 TBLPAG<7:0> TBLPAG<7:0> PSVPAG<7:0> bits Program Counter Select 1 EA PSVPAG Reg 8 bits 15 bits EA TBLPAG Reg 8 bits 16 bits 24-bit EA <15> <14:1> <0> PC<22:1> 0 Data EA<15:0> Data EA<15:0> Data EA<14:0> 0 Byte Select © 2008 Microchip Technology Inc. ...
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... Program Memory ‘Phantom’ Byte (read as ‘0’) © 2008 Microchip Technology Inc. dsPIC30F3014/4013 A set of table instructions are provided to move byte or word-sized data to and from program space. (See Figure 3-4 and Figure 3-5.) 1. TBLRDL: Table Read Low Word: Read the lsw of the program address ...
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... Execution in the last iteration - Execution prior to exiting the loop due to an interrupt - Execution upon re-entering the loop after an interrupt is serviced • Any other iteration of the REPEAT loop allows the instruction accessing data, using PSV, to execute in a single cycle © 2008 Microchip Technology Inc. ...
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... Note: PSVPAG is an 8-bit register, containing bits<22:15> of the program space address (i.e., it defines the page in program space to which the upper half of data space is being mapped). The memory map shown here is for a dsPIC30F4013 device. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 Program Space ...
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... Y data space. A key element of this architecture is that Y space is a subset of X space, and is fully contained within X space. In order to provide an apparent Linear Addressing space, X and Y spaces have contiguous addresses. FIGURE 3-7: dsPIC30F3014/dsPIC30F4013 DATA SPACE MEMORY MAP MSB Address 0x0001 2 Kbyte SFR Space ...
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... FIGURE 3-8: DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE SFR SPACE (Y SPACE) Non-MAC Class Ops (Read/Write) MAC Class Ops (Write) Indirect EA using any W © 2008 Microchip Technology Inc. dsPIC30F3014/4013 SFR SPACE UNUSED Y SPACE UNUSED UNUSED MAC Class Ops (Read) ...
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... Fault. FIGURE 3-9: MSB 15 0001 0003 0x0000 0x0000 0005 0x0000 ® DATA ALIGNMENT LSB 0000 Byte 1 Byte 0 Byte 3 Byte 2 0002 Byte 5 Byte 4 0004 © 2008 Microchip Technology Inc. ...
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... Note push during exception processing concatenates the SRL register to the MSB of the PC prior to the push. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 There is a Stack Pointer Limit register (SPLIM) associ- ated with the Stack Pointer. SPLIM is uninitialized at Reset the case for the Stack Pointer, SPLIM<0> ...
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TABLE 3-3: CORE REGISTER MAP Address SFR Name Bit 15 Bit 14 Bit 13 Bit 12 (Home) W0 0000 W1 0002 W2 0004 W3 0006 W4 0008 W5 000A W6 000C W7 000E W8 0010 W9 0012 W10 0014 ...
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TABLE 3-3: CORE REGISTER MAP (CONTINUED) Address SFR Name Bit 15 Bit 14 Bit 13 Bit 12 (Home) CORCON 0044 — — — US MODCON 0046 XMODEN YMODEN — XMODSRT 0048 XMODEND 004A YMODSRT 004C YMODEND 004E XBREV 0050 ...
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... NOTES: DS70138F-page 34 © 2008 Microchip Technology Inc. ...
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... Register Indirect Register Indirect Post-Modified Register Indirect Pre-Modified Register Indirect with Register Offset The sum of Wn and Wb forms the EA. Register Indirect with Literal Offset © 2008 Microchip Technology Inc. dsPIC30F3014/4013 4.1.1 FILE REGISTER INSTRUCTIONS Most file register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (near data space) ...
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... The only exception to the usage restrictions is for buffers that have a power-of-2 length. As these buffers satisfy the start and end address criteria, they may operate in a Bidirectional mode (i.e., address boundary checks are performed on both the lower and upper address boundaries). © 2008 Microchip Technology Inc. ...
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... MODULO ADDRESSING OPERATION EXAMPLE Byte Address 0x0800 0x0863 Start Addr = 0x0800 End Addr = 0x0863 Length = 0x0032 words © 2008 Microchip Technology Inc. dsPIC30F3014/4013 4.2.2 W ADDRESS REGISTER SELECTION The Modulo and Bit-Reversed Addressing Control reg- registers: ister MODCON<15:0> contains enable flags as well register field to specify the W address registers ...
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... W register that has been designated as the Bit-Reversed Pointer. Sequential Address Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-word Bit-Reversed Buffer N bytes, should not be enabled Bit-Reversed Addressing Bit Locations Swapped Left-to-Right Around Center of Binary Value © 2008 Microchip Technology Inc. ...
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... TABLE 4-2: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address TABLE 4-3: BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER Buffer Size (Words) 1024 512 256 128 © 2008 Microchip Technology Inc. dsPIC30F3014/4013 Bit-Reversed Address Decimal XB<14:0> Bit-Reversed Address Modifier Value A0 Decimal 0x0200 0x0100 ...
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... NOTES: DS70138F-page 40 © 2008 Microchip Technology Inc. ...
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... Using NVMADR Addressing Using Table Instruction User/Configuration Space Select © 2008 Microchip Technology Inc. dsPIC30F3014/4013 5.2 Run-Time Self-Programming (RTSP) RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may erase program memory, 32 instructions (96 bytes time and can write program memory data, 32 instructions (96 bytes time ...
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... NVMKEY register. Refer to Section 5.6 “Programming Operations” for further details. DD Note: The user can also directly write to the NVMADR and NVMADRU registers to specify a program memory address for erasing or programming. © 2008 Microchip Technology Inc. ...
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... MOV #0xAA,W1 MOV W1 NVMKEY , BSET NVMCON,#WR NOP NOP © 2008 Microchip Technology Inc. dsPIC30F3014/4013 4. Write 32 instruction words of data from data RAM “image” into the program Flash write latches. 5. Program 32 instruction words into program Flash. a) Set up NVMCON register for multi-word, program Flash, program, and set WREN bit ...
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... Write PM low word into program latch ; Write PM high byte into program latch ; Block all interrupts with priority <7 for ; next 5 instructions ; ; Write the 0x55 key ; ; Write the 0xAA key ; Start the erase sequence ; Insert two NOPs after the erase ; command is asserted © 2008 Microchip Technology Inc. ...
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TABLE 5-1: NVM REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 NVMCON 0760 WR WREN WRERR NVMADR 0762 NVMADRU 0764 — — — NVMKEY 0766 — — — ...
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... NOTES: DS70138F-page 46 © 2008 Microchip Technology Inc. ...
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... A word write operation should be preceded by an erase of the corresponding memory location(s). The write typically requires complete, but the write time varies with voltage and temperature. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 A program or erase operation on the data EEPROM does not stop the instruction flow. The user is respon- ...
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... Block all interrupts with priority <7 for ; next 5 instructions ; ; Write the 0x55 key ; ; Write the 0xAA key ; Initiate erase sequence ; Block all interrupts with priority <7 for ; next 5 instructions ; ; Write the 0x55 key ; ; Write the 0xAA key ; Initiate erase sequence © 2008 Microchip Technology Inc. ...
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... NOP ; Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle ; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete © 2008 Microchip Technology Inc. dsPIC30F3014/4013 The write does not initiate if the above sequence is not exactly followed (write 0x55 to NVMKEY, write 0xAA to NVMCON, then set WR bit) for each word ...
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... The NVMADR captures last table access address. ; Select data EEPROM for multi word op ; Operate Key to allow program operation ; Block all interrupts with priority <7 for ; next 5 instructions ; Write the 0x55 key ; Write the 0xAA key ; Start write cycle © 2008 Microchip Technology Inc. ...
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... This should be used in applications where excessive writes can stress bits near the specification limit. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 6.5 Protection Against Spurious Write There are conditions when the device may not want to write to the data EEPROM memory ...
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... NOTES: DS70138F-page 52 © 2008 Microchip Technology Inc. ...
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... WR LAT + WR PORT Read LAT Read PORT © 2008 Microchip Technology Inc. dsPIC30F3014/4013 Reads from the latch (LATx), read the latch. Writes to the latch, write the latch (LATx). Reads from the port (PORTx), read the port pins and writes to the port pins, write the latch (LATx) ...
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... OH OL EXAMPLE 7-1: MOV 0xFF00, W0 MOV W0, TRISB NOP BTSS PORTB, #11 Output Multiplexers I/O Cell I/O Pad Input Data PORT WRITE/READ EXAMPLE ; Configure PORTB<15:8> inputs ; and PORTB<7:0> as outputs ; additional instruction cycle ; bit test RB11 and skip if set © 2008 Microchip Technology Inc. ...
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TABLE 7-1: dsPIC30F3014/4013 PORT REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 TRISA 02C0 — — — — PORTA 02C2 — — — — LATA 02C4 — — — — TRISB 02C6 — — — ...
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... State (COS) on selected input pins. This module is capable of detecting input Change-Of-States, even in Sleep mode, when the clocks are disabled. There are external signals (CN0 through CN9, CN17 and CN18) that may be selected (enabled) for generating an interrupt request on a Change-Of-State. DS70138F-page 56 © 2008 Microchip Technology Inc. ...
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TABLE 7-2: INPUT CHANGE NOTIFICATION REGISTER MAP FOR dsPIC30F3014/4013 DEVICES (BITS 15-0) SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name CNEN1 00C0 — — — — — CNEN2 00C2 — — — — — CNPU1 ...
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... NOTES: DS70138F-page 58 © 2008 Microchip Technology Inc. ...
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... The current CPU priority level is explicitly stored in the IPL bits. IPL<3> is present in the CORCON register, whereas IPL<2:0> are present in the STATUS register (SR) in the processor core. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 • INTCON1<15:0>, INTCON2<15:0> Global interrupt control functions are derived from these two registers ...
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... Table 8-1 and Table 8-2 list the interrupt numbers, corresponding interrupt sources and associated vector numbers for the dsPIC30F3014 and dsPIC30F4013 devices, respectively. Note 1: The natural order priority scheme has 0 as the highest priority and 53 as the lowest priority ...
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... TABLE 8-2: dsPIC30F4013 INTERRUPT VECTOR TABLE INT Vector Interrupt Source Number Number Highest Natural Order Priority 0 8 INT0 – External Interrupt IC1 – Input Capture OC1 – Output Compare – Timer IC2 – Input Capture OC2 – Output Compare Timer – Timer 3 ...
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... Level 11, inclusive. The arithmetic error trap (Level 11) falls into this category of traps. ‘Hard’ traps include exceptions of priority Level 12 through Level 15, inclusive. The address error (Level 12), stack error (Level 13) and oscillator error (Level 14) traps fall into this category. © 2008 Microchip Technology Inc. ...
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... STATUS register contains the processor priority level at the time prior to the beginning of the interrupt cycle. The processor then loads the priority level for this © 2008 Microchip Technology Inc. dsPIC30F3014/4013 interrupt into the STATUS register. This action disables all lower priority interrupts until the completion of the Interrupt Service Routine ...
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... If an enabled interrupt request of sufficient priority is received by the interrupt controller, then the standard interrupt request is presented to the processor. At the same time, the processor wakes up from Sleep or Idle and begins execution of the Interrupt Service Routine (ISR) needed to process the interrupt request. © 2008 Microchip Technology Inc. ...
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TABLE 8-3: dsPIC30F3014 INTERRUPT CONTROLLER REGISTER MAP SFR ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name INTCON1 0080 NSTDIS — — — — INTCON2 0082 ALTIVT DISI — — — IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ...
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... TABLE 8-4: dsPIC30F4013 INTERRUPT CONTROLLER REGISTER MAP SFR ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name INTCON1 0080 NSTDIS — — — — INTCON2 0082 ALTIVT DISI — — — IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ADIF IFS1 0086 — — — ...
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... TGATE SOSCO/ T1CK LPOSCEN SOSCI © 2008 Microchip Technology Inc. dsPIC30F3014/4013 These operating modes are determined by setting the appropriate bit(s) in the 16-bit SFR, T1CON. Figure 9-1 presents a block diagram of the 16-bit timer module. 16-Bit Timer Mode: In the 16-Bit Timer mode, the ...
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... Low power • Real-Time Clock interrupts These operating modes are determined by setting the appropriate bit(s) in the T1CON Control register. FIGURE 9-2: RECOMMENDED COMPONENTS FOR TIMER1 LP OSCILLATOR RTC C1 32.768 kHz XTAL pF 100K SOSCI dsPIC30FXXXX SOSCO © 2008 Microchip Technology Inc. ...
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... The TSIDL bit should be cleared to ‘0’ in order for RTC to continue operation in Idle mode. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 9.5.2 RTC INTERRUPTS When an interrupt event occurs, the respective interrupt flag, T1IF, is asserted and an interrupt is generated, if enabled ...
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TABLE 9-1: dsPIC30F3014/4013 TIMER1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — Legend uninitialized bit; — = unimplemented bit, read as ‘0’ Note ...
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... Interrupt on a 32-bit Period register match These operating modes are determined by setting the appropriate bit(s) in the 16-bit T2CON and T3CON SFRs. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 For 32-bit timer/counter operation, Timer2 is the lsw and Timer3 is the msw of the 32-bit timer. ...
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... Timer Configuration bit, T32 (T2CON<3>), must be set to ‘1’ for a 32-bit timer/counter operation. All control bits are respective to the T2CON register. DS70138F-page TMR3 TMR2 MSB LSB Comparator x 32 PR3 PR2 Q D TGATE (T2CON<6> Gate Sync Sync TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 © 2008 Microchip Technology Inc. ...
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... ADC Event Trigger Equal Reset 0 T3IF Event Flag 1 TGATE T3CK Note: T3CK pin does not exist on dsPIC30F3014/4013 devices. The block diagram shown here illustrates the schematic of Timer3 as implemented on the dsPIC30F6014 device. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 PR2 Comparator x 16 TMR2 TGATE TON 1 x ...
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... T3IF bit (IFS0<7>) is asserted and an interrupt is generated, if enabled. In this mode, the T3IF interrupt flag is used as the source of the interrupt. The T3IF bit must be cleared in software. Enabling an interrupt is accomplished via the respective timer interrupt enable bit, T3IE (IEC0<7>). © 2008 Microchip Technology Inc. ...
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TABLE 10-1: dsPIC30F3014/4013 TIMER2/3 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON — TSIDL — T3CON 0112 TON — TSIDL ...
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... NOTES: DS70138F-page 76 © 2008 Microchip Technology Inc. ...
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... TGATE (T4CON<6>) T4CK Note: Timer Configuration bit, T32 (T4CON<3>), must be set to ‘1’ for a 32-bit timer/counter operation. All control bits are respective to the T4CON register. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 The Timer4/5 module is similar in operation to the Timer2/3 module. differences: • The Timer4/5 module does not support the ADC event trigger feature • ...
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... Timer5: 2: TCS = 1 (16-bit counter) 3: TCS = 0, TGATE = 1 (gated time accumulation) DS70138F-page 78 PR4 Comparator x 16 TMR4 TGATE TON 1 x Gate Sync PR5 Comparator x 16 TMR5 TGATE Sync Sync TCKPS<1:0> 2 Prescaler 1, 8, 64, 256 TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 © 2008 Microchip Technology Inc. ...
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... TABLE 11-1: dsPIC30F4013 TIMER4/5 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 TMR4 0114 TMR5HLD 0116 TMR5 0118 PR4 011A PR5 011C T4CON 011E TON — TSIDL — T5CON 0120 TON — TSIDL — Legend uninitialized bit; — = unimplemented bit, read as ‘0’ ...
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... NOTES: DS70138F-page 80 © 2008 Microchip Technology Inc. ...
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... ICxCON register (where x = 1,2,...,N). The dsPIC DSC devices contain capture channels (i.e., the maximum value 8). The dsPIC30F3014 device contains 2 capture channels while the dsPIC30F4013 device contains 4 capture channels. 12.1 Simple Capture Event Mode The simple capture events in the dsPIC30F product family are: • ...
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... IFSx register. Enabling an interrupt is accomplished via the respec- tive Input Capture Channel Interrupt Enable (ICxIE) bit. The capture interrupt enable bit is located in the corresponding IEC Control register. © 2008 Microchip Technology Inc. defined as ...
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... ICSIDL — Legend uninitialized bit; — = unimplemented bit, read as ‘0’ Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. dsPIC30F4013 TABLE 12-2: INPUT CAPTURE REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 IC1BUF ...
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... NOTES: DS70138F-page 84 © 2008 Microchip Technology Inc. ...
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... OCxCON SFR (where x = 1,2,3,...,N). The dsPIC DSC devices contain compare channels (i.e., the maximum value 8). The dsPIC30F3014 device contains 2 compare channels while the dsPIC30F4013 device contains 4 compare channels. OCxRS and OCxR in Figure 13-1 represent the Dual Compare registers. In the Dual Compare mode, the OCxR register is used for the first compare and OCxRS is used for the second compare ...
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... The OCFLT bit (OCxCON<4>) indicates whether a Fault condition has occurred. This state is maintained until both of the following events have occurred: • The external Fault condition has been removed. • The PWM mode has been re-enabled by writing to the appropriate control bits © 2008 Microchip Technology Inc. ...
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... Timer3) is enabled and the TSIDL bit of the selected timer is set to logic ‘0’. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 When the selected TMRx is equal to its respective Period register, PRx, the following four events occur on the next increment cycle: • ...
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... OCSIDL — Legend: — = unimplemented bit, read as ‘0’ Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. TABLE 13-2: dsPIC30F4013 OUTPUT COMPARE REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 OC1RS 0180 ...
Page 91
... Thus, the I C module can operate either as a slave master bus. FIGURE 14-1: PROGRAMMER’S MODEL Bit 15 Bit 15 © 2008 Microchip Technology Inc. dsPIC30F3014/4013 14.1.1 VARIOUS I The following types • slave operation with 7-bit addressing 2 • slave operation with 10-bit addressing 2 • ...
Page 92
... LSB Addr_Match I2CADD Start and Start, Restart, Collision Detect Acknowledge Generation Clock Stretching I2CTRN LSB Reload Control I2CBRG BRG Down Counter F CY Internal Data Bus Read Write Read Write Read Write Read Write Read Write Read © 2008 Microchip Technology Inc. ...
Page 93
... SCL, such that SDA is valid during SCL high. The interrupt pulse is sent on the falling edge of the ninth clock pulse, regardless of the status of the ACK received from the master. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 14.3.2 SLAVE RECEPTION If the R_W bit received is a ‘ ...
Page 94
... C bus have deasserted SCL. This ensures that a write to the SCLREL bit does not violate the minimum high time requirement for SCL. If the STREN bit is ‘0’, a software write to the SCLREL bit is disregarded and has no effect on the SCLREL bit. © 2008 Microchip Technology Inc. overruns from ...
Page 95
... When the interrupt is serviced, the source for the interrupt can be checked by reading the contents of the I2CRCV to determine if the address was device-specific or a general call address. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 2 14. Master Support As a master device, six operations are supported: ...
Page 96
... C, the I2CSIDL bit determines if the module stops or continues on Idle. If I2CSIDL = 0, the module continues operation on assertion of the Idle mode. If I2CSIDL = 1, the module stops on Idle master event Interrupt Service C bus is free (i.e., the P bit is set), the 2 C bus © 2008 Microchip Technology Inc. ...
Page 97
TABLE 14-2: dsPIC30F3014/4013 I C REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 I2CRCV 0200 — — — — I2CTRN 0202 — — — — I2CBRG 0204 — — — — I2CCON 0206 I2CEN ...
Page 98
... NOTES: DS70138F-page 96 © 2008 Microchip Technology Inc. ...
Page 99
... It is compatible with Motorola’s SPI and SIOP interfaces. The dsPIC30F3014 dsPIC30F4013 devices feature one SPI module, SPI1. 15.1 Operating Function Description Each SPI module consists of a 16-bit shift register, SPIxSR (where 2), used for shifting data in and out, and a buffer register, SPIxBUF. A control register, SPIxCON, configures the module ...
Page 100
... Control Select Secondary Prescaler 1:1-1:8 Enable Master Clock SDOx SDIy SDIx SDOy LSb Serial Clock SCKx SCKy Primary Prescaler F CY 1:1, 1:4, 1:16, 1:64 SPI Slave Serial Input Buffer (SPIyBUF) Shift Register (SPIySR) MSb LSb PROCESSOR 2 © 2008 Microchip Technology Inc. ...
Page 101
... The transmitter and receiver stop in Sleep mode. However, register contents are not affected by entering or exiting Sleep mode. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 15.5 SPI Operation During CPU Idle Mode When the device enters Idle mode, all clock sources remain functional. The SPISIDL bit (SPIxSTAT< ...
Page 102
TABLE 15-1: dsPIC30F3014/4013 SPI1 REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name SPI1STAT 0220 SPIEN — SPISIDL — SPI1CON 0222 — FRMEN SPIFSD — DISSDO MODE16 SPI1BUF 0224 Legend: — = unimplemented bit, ...
Page 103
... Data UxTX or UxATX if ALTIO = 1 Parity Note © 2008 Microchip Technology Inc. dsPIC30F3014/4013 16.1 UART Module Overview The key features of the UART module are: • Full-duplex 9-bit data communication • Even, odd or no parity options (for 8-bit data) • One or two Stop bits • ...
Page 104
... Receive Buffer Control 8-9 Load RSR to Buffer Receive Shift Register (UxRSR) 16 Divider 16x Baud Clock from Baud Rate Generator Read Read Write UxMODE UxSTA – Generate Flags – Generate Interrupt – Shift Data Characters Control Signals UxRXIF © 2008 Microchip Technology Inc. ...
Page 105
... The STSEL bit determines whether one or two Stop bits are used during data transmission. The default (power-on) setting of the UART is 8 bits, no parity and 1 Stop bit (typically represented 1). © 2008 Microchip Technology Inc. dsPIC30F3014/4013 16.3 Transmitting Data 16.3.1 ...
Page 106
... UxRSR needs to transfer the character to the buffer. Once OERR is set, no further data is shifted in UxRSR (until the OERR bit is cleared in software or a Reset occurs). The data held in UxRSR and UxRXREG remains valid. © 2008 Microchip Technology Inc. RXB) ...
Page 107
... FERR bit set. The Break character is loaded into the buffer. No further reception can occur until a Stop bit is received. Note that RIDLE goes high when the Stop bit has not yet been received. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 16.6 Address Detect Mode Setting the ADDEN bit (UxSTA< ...
Page 108
... UART OPERATION DURING CPU IDLE MODE For the UART, the USIDL bit determines if the module stops or continues operation when the device enters Idle mode. If USIDL = 0, the module continues operation during Idle mode. If USIDL = 1, the module stops on Idle. © 2008 Microchip Technology Inc. ...
Page 109
TABLE 16-1: dsPIC30F3014/4013 UART1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 U1MODE 020C UARTEN — USIDL — U1STA 020E UTXISEL — — — UTXBRK UTXEN U1TXREG 0210 — — — — U1RXREG ...
Page 110
... NOTES: DS70138F-page 108 © 2008 Microchip Technology Inc. ...
Page 111
... Programmable link to input capture module (IC2, for both CAN1 and CAN2) for time-stamping and network synchronization • Low-power Sleep and Idle mode © 2008 Microchip Technology Inc. dsPIC30F3014/4013 The CAN bus module consists of a protocol engine and message buffering/control. The CAN protocol engine handles all functions for receiving and transmitting messages on the CAN bus ...
Page 112
... RXF3 c Acceptance Filter e (2) RXF4 p t Acceptance Filter (2) RXF5 ( Identifier Data Field Receive RERRCNT Error Counter TERRCNT Transmit Err Pas Error Bus Off Counter Protocol Finite State Machine Bit Timing Bit Timing Logic Generator (1) CiRX © 2008 Microchip Technology Inc. ...
Page 113
... Module Disable mode. The I/O pins revert to normal I/O function when the module is in the Module Disable mode. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 The module can be programmed to apply a low-pass filter function to the CiRX input line while the module or the CPU is in Sleep mode. The WAKFIL bit (CiCFG2< ...
Page 114
... End-of-Frame (EOF) field. Reading the RXnIF flag indicates which receive buffer caused the interrupt. • Wake-up Interrupt: The CAN module has woken up from Disable mode or the device has woken up from Sleep mode. © 2008 Microchip Technology Inc. ...
Page 115
... SOF occurs. When TXREQ is set, the TXABT (CiTXnCON<6>), TXLARB (CiTXnCON<5>) and TXERR (CiTXnCON<4>) flag bits are automatically cleared. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 Setting TXREQ bit simply flags a message buffer as enqueued for transmission. When the module detects an available bus, it begins transmitting the message which has been determined to have the highest priority ...
Page 116
... definition, the nominal bit time has a minimum and a maximum the minimum nominal bit time is 1 μsec corresponding to a maximum bit rate of 1 MHz. Phase Phase Segment 1 Segment 2 Sample Point . Also, by definition, Q Sync © 2008 Microchip Technology Inc. ...
Page 117
... SEG1PH<2:0> (CiCFG2<5:3>), and Phase2 Seg is initialized by setting SEG2PH<2:0> (CiCFG2<10:8>). The following requirement must be fulfilled while setting the lengths of the phase segments: Prop Seg + Phase1 Seg > = Phase2 Seg © 2008 Microchip Technology Inc. dsPIC30F3014/4013 17.6.5 SAMPLE POINT The sample point is the point of time at which the bus ...
Page 118
... TABLE 17-1: dsPIC30F4013 CAN1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 C1RXF0SID 0300 — — — C1RXF0EIDH 0302 — — — — C1RXF0EIDL 0304 Receive Acceptance Filter 0 Extended Identifier<5:0> C1RXF1SID 0308 — — — C1RXF1EIDH 030A — — — ...
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... TABLE 17-1: dsPIC30F4013 CAN1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 C1TX1B1 0356 Transmit Buffer 1 Byte 1 C1TX1B2 0358 Transmit Buffer 1 Byte 3 C1TX1B3 035A Transmit Buffer 1 Byte 5 C1TX1B4 035C Transmit Buffer 1 Byte 7 C1TX1CON 035E — — — — C1TX0SID 0360 Transmit Buffer 0 Standard Identifier< ...
Page 120
... NOTES: DS70138F-page 118 © 2008 Microchip Technology Inc. ...
Page 121
... CSDOM control bit. This allows other devices to place data on the serial bus during transmission periods not used by the DCI module. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 18.2.3 CSDI PIN The serial data input (CSDI) pin is configured as an input only pin when the module is enabled ...
Page 122
... DCI Mode Selection bits Receive Buffer Registers w/Shadow Transmit Buffer Registers w/Shadow DS70138F-page 120 BCG Control bits Sample Rate /4 Generator Frame Synchronization Generator DCI Buffer Control Unit 15 DCI Shift Register SCKD CSCK FSD COFS 0 CSDI CSDO © 2008 Microchip Technology Inc. ...
Page 123
... Note: The COFSG control bits have no effect in AC-Link mode since the frame length is set to 256 CSCK periods by the protocol. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 18.3.4 FRAME SYNC MODE CONTROL BITS The type of Frame Sync signal is selected using the ...
Page 124
... Frame Sync pulses until the data frame transfer has completed. LSB S12 S12 S12 Tag Tag Tag bit 2 bit 1 LSb MSb bit 14 bit 13 MSB LSB MSB 2 S protocol does not specify word length – this LSB © 2008 Microchip Technology Inc. ...
Page 125
... DCI module. 2: When the CSCK signal is applied externally (CSCKD = 1), the external clock high and low times must meet the device timing requirements. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 EQUATION 18-2: The required bit clock frequency is determined by the system sampling rate and frame size. Typical bit clock ...
Page 126
... Furthermore, assume that data is only received during slot #0 but is transmitted during slot #0 and slot #1. In this case, the buffer control unit counter would be incremented twice during a data frame but only one receive register location would be filled with data. © 2008 Microchip Technology Inc. ...
Page 127
... SLOT status bits to determine what data should be loaded into the buffer registers to resynchronize the software with the DCI module. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 18.3.16 TRANSMIT STATUS BITS There are two transmit status bits in the DCISTAT SFR. ...
Page 128
... This trun- cation of the time slots limits the A/D and DAC data to 16 bits but permits proper data alignment in the TXBUF and RXBUF registers. Each RXBUF and TXBUF register contains one data time slot value. © 2008 Microchip Technology Inc. ...
Page 129
... Synchronization signal marks the boundary of a new data word transfer. The user must also select the frame length and data word size using the COFSG and WS control bits in the DCICON2 SFR. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 2 18.7 FRAME AND DATA WORD ...
Page 130
TABLE 18-2: dsPIC30F3014/4013 DCI REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 DCICON1 0240 DCIEN — DCISIDL — DCICON2 0242 — — — — DCICON3 0244 — — — — DCISTAT 0246 — — — ...
Page 131
... The ADCHS, ADPCFG and ADCSSL registers allow the application to configure AN13-AN15 as analog input pins. Since these pins are not physically present on the device, conversion results from these pins will read ‘0’. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 The A/D module has six 16-bit registers: • ...
Page 132
... Note: The ADCHS, ADPCFG and ADCSSL reg- isters allow the application to configure AN13-AN15 as analog input pins. Since these pins are not physically present on the device, conversion results from these pins read ‘0’. © 2008 Microchip Technology Inc. ...
Page 133
... There are 64 possible options for T EQUATION 19-1: ADC CONVERSION CLOCK (0.5*(ADCS<5:0> © 2008 Microchip Technology Inc. dsPIC30F3014/4013 The internal RC oscillator is selected by setting the ADRC bit. For correct ADC conversions, the ADC conversion clock (T ) must be selected to ensure a minimum T AD time of 334 nsec (for V “ ...
Page 134
... REF circuit. DS70138F-page 132 R Max V Temperature DD s 2.5 kΩ 4.5V to 5.5V -40°C to +85°C 2.5 kΩ 3.0V to 5.5V -40°C to +125°C Channels Configuration REF REF CH X ANx S/H ADC REF REF ANx S/H ADC ANx REF © 2008 Microchip Technology Inc. ...
Page 135
... Set SSRC<2.0> = 111 in the ADCON1 register to enable the auto-convert option. • Enable automatic sampling by setting the ASAM control bit in the ADCON1 register. • Write the SMPI<3.0> control bits in the ADCON2 register for the desired number of conversions between interrupts. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 ...
Page 136
... The inter- nal holding capacitor will discharged state prior ), the S to each sample operation ≤ 250Ω Sampling Switch LEAKAGE V = 0.6V T ± 500 nA PIN HOLD ≤ 3 kΩ HOLD = DAC capacitance = negligible if Rs ≤ 2.5 kΩ. © 2008 Microchip Technology Inc. ...
Page 137
... Signed Integer d11 d11 d11 d11 d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 Integer 0 © 2008 Microchip Technology Inc. dsPIC30F3014/4013 If the A/D interrupt is enabled, the device wakes up from Sleep. If the A/D interrupt is not enabled, the A/D module is then turned off, although the ADON bit remains set ...
Page 138
... Any external components connected (via high-impedance analog input pin (capacitor, Zener diode, etc.) should have very little leakage current at the pin. and V as ESD DD SS and the input voltage exceeds this SS © 2008 Microchip Technology Inc. ...
Page 139
TABLE 19-2: A/D CONVERTER REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name ADCBUF0 0280 — — — — ADCBUF1 0282 — — — — ADCBUF2 0284 — — — — ADCBUF3 0286 — — — ...
Page 140
... NOTES: DS70138F-page 138 © 2008 Microchip Technology Inc. ...
Page 141
... In the Idle mode, the clock sources are still active but the CPU is shut off. The RC oscillator option saves system cost while the LP crystal option saves power. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 20.1 Oscillator System Overview The dsPIC30F oscillator system has the following modules and features: • ...
Page 142
... RC oscillator Note 1: dsPIC30F maximum operating frequency of 120 MHz must be met oscillator can be conveniently shared as system clock, as well as Real-Time Clock for Timer1. 3: Requires external R and C. Frequency operation MHz. DS70138F-page 140 Description (1) (2) (1) (1) (1) (3) /4 output OSC (3) © 2008 Microchip Technology Inc. ...
Page 143
... FIGURE 20-1: OSCILLATOR SYSTEM BLOCK DIAGRAM OSC1 Primary Oscillator OSC2 POR Done SOSCO 32 kHz LP Oscillator SOSCI © 2008 Microchip Technology Inc. dsPIC30F3014/4013 F PLL PLL x4, x8, x16 PLL Lock Primary Osc Primary Oscillator Stability Detector Oscillator Start-up Timer Clock Switching Secondary Osc ...
Page 144
... FOS<2:0> FPR<4:0> cycles before releasing the OSC . The T time is involved OST OST OSC2 Function OSC2 OSC2 OSC2 OSC2 OSC2 OSC2 OSC2 OSC2 OSC2 I OSC2 OSC2 CLKO CLKO I OSC2 (Notes (Notes (Notes © 2008 Microchip Technology Inc. ...
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... Table 20-4). If OSCCON<14:12> are set to ‘111’ and FPR<4:0> are set to ‘00101’, ‘00110’ or ‘00111’, then a PLL multiplier (respectively) is applied. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 Note: When a 16x PLL is used, the FRC frequency must not be tuned to a frequency greater than 7 ...
Page 146
... To write to the OSCCON high byte, the following instructions must be executed without any other instructions in between: Byte Write “0x78” to OSCCON high Byte Write “0x9A” to OSCCON high Byte write is allowed for one instruction cycle. Write the desired value or use bit manipulation instruction. © 2008 Microchip Technology Inc. ...
Page 147
... Unimplemented: Read as ‘0’ © 2008 Microchip Technology Inc. dsPIC30F3014/4013 Note: The description of the OSCCON and OSCTUN SFRs, as well as the FOSC Con- figuration register provided in this section are applicable only to the dsPIC30F3014 and dsPIC30F4013 dsPIC30F product family. R-y U-0 R/W-y — U-0 R/W-0 U-0 — ...
Page 148
... OSWEN: Oscillator Switch Enable bit 1 = Request oscillator switch to selection specified by NOSC<2:0> bits 0 = Oscillator switch is complete Reset on POR or BOR. Reset after a successful clock switch. Reset after a redundant clock switch. Reset after FSCM switches the oscillator to (Group 1) FRC. DS70138F-page 146 © 2008 Microchip Technology Inc. ...
Page 149
... Center frequency, oscillator is running at calibrated frequency 1111 = 1110 = 1101 = 1100 = 1011 = 1010 = 1001 = 1000 = Minimum frequency © 2008 Microchip Technology Inc. dsPIC30F3014/4013 U-0 U-0 U-0 — — — U-0 R/W-0 R/W-0 — TUN<3:0> Unimplemented bit, read as ‘0’ ...
Page 150
... FPR<4:0>: Oscillator Selection within Primary Group bits (see Table 20-2) DS70138F-page 148 — — — R/P — — R/P R/P R/P FPR<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2008 Microchip Technology Inc — — bit 16 R/P R/P FOS<2:0> bit 8 R/P R/P bit Bit is unknown ...
Page 151
... The POR pulse resets a POR timer and places the device in the Reset state. The POR also selects the device clock source identified by the oscillator configuration fuses. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 Different registers are affected in different ways by var- ious Reset conditions. Most registers are not affected by a WDT wake-up since this is viewed as the resump- tion of normal operation ...
Page 152
... INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset FIGURE 20-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset DS70138F-page 150 T OST T PWRT T OST T PWRT T OST T PWRT ) DD ): CASE CASE 2 DD © 2008 Microchip Technology Inc. ...
Page 153
... Refer to the Electrical Specifications in the specific device data sheet for BOR voltage limit specifications. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 A BOR generates a Reset pulse, which resets the device. The BOR selects the clock source based on the device Configuration bit values (FOS< ...
Page 154
... Note 1: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector. DS70138F-page 152 TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR ( TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR ( © 2008 Microchip Technology Inc. ...
Page 155
... In some devices, the LVD threshold voltage may be applied externally on the LVDIN pin. The LVD module is enabled by setting the LVDEN bit (RCON<12>). © 2008 Microchip Technology Inc. dsPIC30F3014/4013 20.7 Power-Saving Modes There are two power-saving states that can be entered through the execution of a special instruction, PWRSAV ...
Page 156
... For additional information, please refer to the Programming Specifications of the device. Note: If the code protection Configuration fuse bits (FGS<GCP> and FGS<GWRP>) have been programmed, an erase of the entire code-protected device is only possible at voltages V © 2008 Microchip Technology Inc. ≥ 4.5V. DD ...
Page 157
... Note: In the dsPIC30F3014 device, the T4MD, T5MD, IC7MD, IC8MD, OC3MD, OC4MD and DCIMD are readable and writable, and are read as “1” when set. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 20.10 In-Circuit Debugger ® When MPLAB ICD 2 is selected as a debugger, the in- circuit debugging functionality is enabled ...
Page 158
TABLE 20-7: SYSTEM INTEGRATION REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name RCON 0740 TRAPR IOPUWR BGST LVDEN OSCCON 0742 — COSC<2:0> — OSCTUN 0744 — — — — — (4) (4) PMD1 ...
Page 159
... The file register specified by the value ‘f’ • The destination, which could either be the file register ‘f’ or the W0 register, which is denoted as ‘WREG’ © 2008 Microchip Technology Inc. dsPIC30F3014/4013 Most bit-oriented instructions (including simple rotate/ shift instructions) have two operands: • ...
Page 160
... Moreover, double-word moves require two cycles. The instructions execute in two instruction cycles. Note: For more details on the instruction set, refer to the “Programmer’s Reference Manual”. Description © 2008 Microchip Technology Inc. double-word ...
Page 161
... Y data space prefetch address register for DSP instructions ∈ {[W10]+=6, [W10]+=4, [W10]+=2, [W10], [W10]-=6, [W10]-=4, [W10]-=2, [W11]+=6, [W11]+=4, [W11]+=2, [W11], [W11]-=6, [W11]-=4, [W11]-=2, [W11+W12], none} Y data space prefetch destination register for DSP instructions ∈ {W4..W7} Wyd © 2008 Microchip Technology Inc. dsPIC30F3014/4013 Description DS70138F-page 159 ...
Page 162
... Branch if Accumulator A Overflow Branch if Accumulator B Overflow Branch if Overflow Branch if Accumulator A Saturated Branch if Accumulator B Saturated Branch Unconditionally Branch if Zero Computed Branch Bit Set f Bit Set Ws Write C bit to Ws<Wb> Write Z bit to Ws<Wb> © 2008 Microchip Technology Inc Status Flags Cycles Affected 1 1 OA,OB,SA, C,DC,N,OV,Z 1 ...
Page 163
... DEC2 DEC2 f DEC2 f,WREG DEC2 Ws,Wd 28 DISI DISI #lit14 © 2008 Microchip Technology Inc. dsPIC30F3014/4013 # of Description Words Bit Toggle f Bit Toggle Ws Bit Test f, Skip if Clear Bit Test Ws, Skip if Clear Bit Test f, Skip if Set Bit Test Ws, Skip if Set Bit Test f Bit Test Bit Test Bit Test Ws< ...
Page 164
... Move f to WREG Move 16-Bit Literal to Wn Move 8-Bit Literal to Wn Move Move Move WREG to f Move Double from W(ns):W(ns+ Move Double from Ws to W(nd+1):W(nd) Prefetch and Store Accumulator © 2008 Microchip Technology Inc Status Flags Cycles Affected 1 18 N,Z,C,OV 1 ...
Page 165
... RLNC f,WREG RLNC Ws,Wd 65 RRC RRC f RRC f,WREG RRC Ws,Wd © 2008 Microchip Technology Inc. dsPIC30F3014/4013 # of Description Words Multiply Accumulator Square Wm to Accumulator -(Multiply Wm by Wn) to Accumulator Multiply and Subtract from Accumulator {Wnd+1, Wnd} = Signed(Wb) * Signed(Ws) {Wnd+1, Wnd} = Signed(Wb) * Unsigned(Ws) {Wnd+1, Wnd} = Unsigned(Wb) * ...
Page 166
... Wn = Nibble Swap Byte Swap Wn Read Prog<23:16> to Wd<7:0> Read Prog<15:0> Write Ws<7:0> to Prog<23:16> Write Ws to Prog<15:0> Unlink Frame Pointer .XOR. WREG WREG = f .XOR. WREG Wd = lit10 .XOR .XOR .XOR. lit5 Wnd = Zero-Extend Ws © 2008 Microchip Technology Inc Status Flags Cycles Affected N,Z ...
Page 167
... PICSTART Plus Development Programmer - MPLAB PM3 Device Programmer - PICkit™ 2 Development Programmer • Low-Cost Demonstration and Development Boards and Evaluation Kits © 2008 Microchip Technology Inc. dsPIC30F3014/4013 22.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market ...
Page 168
... MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. ® DSCs on an instruction © 2008 Microchip Technology Inc. ...
Page 169
... REAL ICE offers significant advantages over competi- tive emulators including low-cost, full-speed emulation, real-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 22.9 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD ...
Page 170
... K L security ICs, CAN ® IrDA , PowerSmart battery management, SEEVAL evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. © 2008 Microchip Technology Inc. ® ...
Page 171
... Temp Range DD 4.5-5.5V -40°C to 85°C 4.5-5.5V -40°C to 125°C 3.0-3.6V -40°C to 85°C 3.0-3.6V -40°C to 125°C 2.5-3.0V -40°C to 85°C © 2008 Microchip Technology Inc. dsPIC30F3014/4013 (except V and MCLR) (Note 1) ..................................... -0. ....................................................................................................... 0V to +13.25V ) .......................................................................................................... ± > ...................................................................................................± pin, inducing currents greater than 80 mA, may cause latch-up. ...
Page 172
... TABLE 23-2: THERMAL OPERATING CONDITIONS Rating dsPIC30F3014-30I dsPIC30F4013-30I Operating Junction Temperature Range Operating Ambient Temperature Range dsPIC30F3014-20E dsPIC30F4013-20E Operating Junction Temperature Range Operating Ambient Temperature Range Power Dissipation: Internal chip power dissipation: × ∑ – I INT I/O Pin power dissipation: ...
Page 173
... All I/O pins are configured as inputs and pulled to V MCLR = V , WDT, FSCM, LVD and BOR are disabled. CPU, SRAM, program memory and data memory DD are operational. No peripheral modules are operating. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 ) DD Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40° ...
Page 174
... MIPS LPRC (512 kHz) 1.8 MIPS FRC (7.37 MHz) 4 MIPS 10 MIPS 20 MIPS 30 MIPS © 2008 Microchip Technology Inc. ...
Page 175
... LVD, BOR, WDT, etc. are all switched off. The Δ current is the additional current consumed when the module is enabled. This current should be 2: added to the base I current. PD © 2008 Microchip Technology Inc. dsPIC30F3014/4013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T ≤ +85°C for Industrial ...
Page 176
... Units Conditions bus disabled bus enabled bus disabled V SM bus enabled μ 5V PIN SS μA ≤ V ≤ PIN DD Pin at high-impedance μA ≤ V ≤ PIN DD Pin at high-impedance μA ≤ V ≤ PIN DD μA ≤ V ≤ XT PIN DD and LP Osc mode © 2008 Microchip Technology Inc. ...
Page 177
... These parameters are characterized but not tested in manufacturing. FIGURE 23-1: LOW-VOLTAGE DETECT CHARACTERISTICS V DD LV10 LVDIF (LVDIF set by hardware) © 2008 Microchip Technology Inc. dsPIC30F3014/4013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T (1) Min ...
Page 178
... V — — V — — V — 2.65 V — 2.86 V — 2.97 V — 3.18 V — 3.50 V — 3.71 V — 3.82 V — 4.03 V — 4.24 V — 4.45 V — 4.77 V — — V (Device not in Brown-out Reset) Power-up Time-out © 2008 Microchip Technology Inc. ...
Page 179
... During Programming EB DD Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. 2: These parameters are characterized but not tested in manufacturing. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T ...
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... Section 23.1 “DC Characteristics”. Load Condition 2 – for OSC2 Pin L Legend 464Ω for all pins except OSC2 for OSC2 output OS20 OS30 OS30 OS25 OS40 ≤ +85°C for Industrial A ≤ +125°C for Extended OS31 OS31 OS41 © 2008 Microchip Technology Inc. ...
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... Measurements are taken ERC modes. The CLKO signal is measured on the OSC2 pin. CLKO is low for the Q1-Q2 period (1/2 T © 2008 Microchip Technology Inc. dsPIC30F3014/4013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40° ...
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... V = 4 ≤ +85° 3 ≤ +85° 4 ≤ +125° 4 MIPS MIPS (3) (3) (3) w/PLL x8 w/PLL x16 — — 8.0 16.0 20.0 — — — 8.0 16.0 20.0 — © 2008 Microchip Technology Inc. ...
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... Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature Param Characteristic No. (1) LPRC @ Freq. = 512 kHz OS65A OS65B OS65C Note 1: Change of LPRC frequency as V © 2008 Microchip Technology Inc. dsPIC30F3014/4013 -40°C ≤ -40°C ≤ Min Typ Max Units (1) -40°C ≤ T — — ...
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... Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T ≤ +85°C for Industrial Operating temperature A -40°C ≤ T ≤ +125°C for Extended A (1,2,3) (4) Min Typ Max — — — — — — CY Units Conditions OSC © 2008 Microchip Technology Inc. ...
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... TIMER TIMING CHARACTERISTICS V DD SY12 MCLR Internal POR SY11 PWRT Time-out SY30 Oscillator Time-out Internal Reset Watchdog Timer Reset I/O Pins SY35 FSCM Delay Note: Refer to Figure 23-3 for load conditions. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 SY10 SY20 SY13 SY13 DS70138F-page 183 ...
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... Band Gap Stable ≤ +85°C for Industrial A ≤ +125°C for Extended A Conditions Defined as the time between the instant that the band gap is enabled and the moment that the band gap reference voltage is stable (RCON<13> status bit) © 2008 Microchip Technology Inc. ...
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... TCS (T1CON<1>) TA20 T Delay from External TxCK Clock CKEXTMRL Edge to Timer Increment Note 1: Timer1 is a Type A. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 Tx11 Tx10 Tx15 OS60 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40° ...
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... T — CY ≤ +85°C for Industrial A ≤ +125°C for Extended A Max Units Conditions — ns Must also meet parameter TC15 — ns Must also meet parameter TC15 — prescale value (1, 8, 64, 256) 1.5 — © 2008 Microchip Technology Inc. ...
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... Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 IC10 IC11 IC15 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40° ...
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... OC20 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) (2) Min Typ Max Units — — — — ns -40°C ≤ T ≤ +85°C for Industrial A -40°C ≤ T ≤ +125°C for Extended A Conditions © 2008 Microchip Technology Inc. ...
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... CSCK (SCKE = 0) CSCK (SCKE = 1) COFS CS55 CS56 CS35 CS51 CS50 HIGH-Z CSDO CSDI Note: Refer to Figure 23-3 for load conditions. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 2 S MODES) TIMING CHARACTERISTICS CS11 CS10 CS21 CS20 MSb CS30 MSb IN CS40 CS41 CS20 CS21 ...
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... Industrial A ≤ +125°C for Extended A Units Conditions Note 1 ns Note © 2008 Microchip Technology Inc. ...
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... DCI MODULE (AC-LINK MODE) TIMING CHARACTERISTICS BIT_CLK (CSCK) CS61 CS60 SYNC (COFS) CS80 MSb LSb SDOx (CSDO) MSb In SDIx (CSDI) CS65 CS66 © 2008 Microchip Technology Inc. dsPIC30F3014/4013 CS62 CS21 CS71 CS72 CS76 CS76 CS75 CS20 CS70 CS75 LSb DS70138F-page 191 ...
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... SP20 MSb Bit SP30 Bit -40°C ≤ T ≤ +85°C for Industrial A -40°C ≤ T ≤ +125°C for Extended A Units Conditions Bit clock is input ns ns μs Note 1 μs Note 1 μs Note pF LOAD pF LOAD DD ns LSb LSb In © 2008 Microchip Technology Inc. ...
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... SP36 SCK X (CKP = 0) SP11 SCK X (CKP = 1) SDO MSb X SP40 SP30,SP31 SDI X MSb In SP41 Note: Refer to Figure 23-3 for load conditions. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) (2) Min Typ ( — — ...
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... Industrial A -40°C ≤ T ≤ +125°C for Extended A Max Units Conditions — ns — ns — ns See parameter DO32 — ns See parameter DO31 — ns See parameter DO32 — ns See parameter DO31 30 ns — ns — ns — ns © 2008 Microchip Technology Inc. ...
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... These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: Assumes 50 pF load on all SPI pins. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 SP70 SP72 SP73 SP73 ...
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... SP50 SCK X (CKP = 0) SP71 SCK X (CKP = 1) MSb SDO X SP30,SP31 SDI SDI X MSb In SP41 SP40 Note: Refer to Figure 23-3 for load conditions. DS70138F-page 196 SP70 SP72 SP73 SP35 SP73 SP72 SP52 Bit LSb Bit LSb In SP52 SP51 © 2008 Microchip Technology Inc. ...
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... The minimum clock period for SCKx is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPI pins. © 2008 Microchip Technology Inc. dsPIC30F3014/4013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) ...
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... C pins (for 1 MHz mode only). IM34 IM33 Stop Condition IM21 IM33 IM45 ≤ +85°C for Industrial A ≤ +125°C for Extended A Units Conditions μs μs μs μs μs μ specified from 10 to 400 C)” © 2008 Microchip Technology Inc. ...