DSPIC30F4013-20E/PT Microchip Technology, DSPIC30F4013-20E/PT Datasheet - Page 18

• Manufacturer Part Number: DSPIC30F4013-20E/PT
• Description: IC DSPIC MCU/DSP 48K 44TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4013-20E/PT

• Program Memory Type: FLASH
• Program Memory Size: 48KB (16K x 24)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, POR, PWM, WDT
• Number Of I /o: 30
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 30
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
• Minimum Operating Temperature: - 40 C
• Package: 44TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 13-chx12-bit
• Number Of Timers: 5
• Core Frequency: 20MHz
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 30
• Flash Memory Size: 48KB
• Supply Voltage Range: 2.5V To 5.5V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC30F006 - MODULE SKT FOR DSPIC30F 44TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F401320EPT

5.7.2
System operation Configuration bits are inherently
different than all other memory cells. Unlike code
memory,
Configuration bits, the system operation bits cannot be
erased. If the chip is erased with the ERASEB
command, the system-operation bits retain their
previous value. Consequently, you should make no
assumption about the value of the system operation
bits. They should always be programmed to their
desired setting.
Configuration bits are programmed as a single word at
a time using the PROGC command. The PROGC
command specifies the configuration data and
Configuration register address. When Configuration
bits are programmed, any unimplemented bits must be
programmed with a ‘0’, and any reserved bits must be
programmed with a ‘1’.
Four PROGC commands are required to program all the
Configuration bits.
Configuration bit programming.
5.7.3
Once the Configuration bits are programmed, the
contents of memory should be verified to ensure that
the programming was successful. Verification requires
the Configuration bits to be read back and compared
against the copy held in the programmer’s buffer. The
READD command reads back the programmed
Configuration
programming was successful.
Any unimplemented Configuration bits are read-only
and read as ‘0’.
DS70102K-page 18
Note:
PROGRAMMING METHODOLOGY
If the General Code Segment Code
Protect (GCP) bit is programmed to ‘0’,
code memory is code-protected and can-
not
be verified before enabling read protec-
tion. See
Configuration Bits”
about code-protect Configuration bits.
PROGRAMMING VERIFICATION
data
bits
be
Figure 5-5
EEPROM
read.
Section 5.7.4 “Code-Protect
and
illustrates the flowchart of
verifies
Code
for more information
and
memory
whether
code-protect
must
the
5.7.4
The FBS, FSS and FGS Configuration registers are
special Configuration registers that control the size and
level of code protection for the Boot Segment, Secure
Segment and General Segment, respectively. For each
segment, two main forms of code protection are
provided. One form prevents code memory from being
written (write protection), while the other prevents code
memory from being read (read protection).
The BWRP, SWRP and GWRP bits control write
protection; and BSS<2:0>, SSS<2:0> and GSS<1:0>
bits control read protection. The Chip Erase ERASEB
command sets all the code protection bits to ‘1’, which
allows the device to be programmed.
When write protection is enabled, any programming
operation to code memory will fail. When read
protection is enabled, any read from code memory will
cause a ‘0x0’ to be read, regardless of the actual
contents of code memory. Since the programming
executive always verifies what it programs, attempting
to program code memory with read protection enabled
will also result in failure.
It is imperative that all code protection bits are ‘1’ while
the device is being programmed and verified. Only after
the device is programmed and verified should any of
the above bits be programmed to ‘0’ (see
“Configuration Bits
In addition to code memory protection, parts of data
EEPROM and/or data RAM can be configured to be
accessible only by code resident in the Boot Segment
and/or Secure Segment. The sizes of these “reserved”
sections are user-configurable, using the EBS,
RBS<1:0>, ESS<1:0> and RSS<1:0> bits.
Note 1: All bits in the FBS, FSS and FGS
2: If any of the code-protect bits in FBS,
CODE-PROTECT CONFIGURATION
BITS
Configuration registers can only be
programmed to a value of ‘0’. ERASEB is
the only way to reprogram code-protect
bits from ON (‘0’) to OFF (‘1’).
FSS, or FGS are clear, the entire device
must be erased before it can be
reprogrammed.
Programming”).
© 2010 Microchip Technology Inc.
Section 5.7