DSPIC30F4013-20E/PT Microchip Technology, DSPIC30F4013-20E/PT Datasheet - Page 34

• Manufacturer Part Number: DSPIC30F4013-20E/PT
• Description: IC DSPIC MCU/DSP 48K 44TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4013-20E/PT

• Program Memory Type: FLASH
• Program Memory Size: 48KB (16K x 24)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, POR, PWM, WDT
• Number Of I /o: 30
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 30
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
• Minimum Operating Temperature: - 40 C
• Package: 44TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 13-chx12-bit
• Number Of Timers: 5
• Core Frequency: 20MHz
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 30
• Flash Memory Size: 48KB
• Supply Voltage Range: 2.5V To 5.5V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC30F006 - MODULE SKT FOR DSPIC30F 44TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F401320EPT

11.0
11.1
ICSP mode is a special programming protocol that
allows you to read and write to the dsPIC30F program-
ming executive. The ICSP mode is the second (and
slower) method used to program the device. This mode
also has the ability to read the contents of executive
memory to determine whether the programming exec-
utive is present. This capability is accomplished by
applying control codes and instructions serially to the
device using pins PGC and PGD.
In ICSP mode, the system clock is taken from the PGC
pin, regardless of the device’s oscillator Configuration
bits. All instructions are first shifted serially into an
internal buffer, then loaded into the Instruction register
and executed. No program fetching occurs from
internal memory. Instructions are fed in 24 bits at a
time. PGD is used to shift data in and PGC is used as
both the serial shift clock and the CPU execution clock.
Data is transmitted on the rising edge and latched on
the falling edge of PGC. For all data transmissions, the
Least Significant bit (LSb) is transmitted first.
11.2
Upon entry into ICSP mode, the CPU is idle. Execution
of the CPU is governed by an internal state machine. A
4-bit control code is clocked in using PGC and PGD,
and this control code is used to command the CPU
(see
The SIX control code is used to send instructions to the
CPU for execution, while the REGOUT control code is
used to read data out of the device via the VISI register.
The operation details of ICSP mode are provided in
Section 11.2.1 “SIX Serial Instruction Execution”
and
Execution”.
DS70102K-page 34
Note 1: During ICSP operation, the operating
Table
Section 11.2.2 “REGOUT Serial Instruction
2: Because ICSP is slower, it is recom-
ICSP™ MODE
ICSP Mode
ICSP Operation
11-1).
frequency of PGC must not exceed
5 MHz.
mended that only Enhanced ICSP (E-
ICSP) mode be used for device program-
ming, as described in
“Overview
Process”.
of
the
Programming
Section 5.1
TABLE 11-1:
11.2.1
The SIX control code allows execution of dsPIC30F
assembly instructions. When the SIX code is received,
the CPU is suspended for 24 clock cycles as the
instruction is then clocked into the internal buffer. Once
the instruction is shifted in, the state machine allows it
to be executed over the next four clock cycles. While
the received instruction is executed, the state machine
simultaneously shifts in the next 4-bit command (see
Figure
0000b
0001b
0010b-1111b N/A
Note 1: Coming out of the ICSP entry sequence,
Control
Code
4-bit
11-2).
2: TBLRDH, TBLRDL, TBLWTH and TBLWTL
SIX SERIAL INSTRUCTION
EXECUTION
the first 4-bit control code is always
forced to SIX and a forced NOP instruc-
tion is executed by the CPU. Five addi-
tional PGC clocks are needed on start-
up, thereby resulting in a 9-bit SIX com-
mand instead of the normal 4-bit SIX
command. After the forced SIX is clocked
in, ICSP operation resumes as normal
(the next 24 clock cycles load the first
instruction word to the CPU). See
Figure 11-1
instructions must be followed by a NOP
instruction.
SIX
REGOUT
Mnemonic
CPU CONTROL CODES IN
ICSP™ MODE
© 2010 Microchip Technology Inc.
for details.
Shift in 24-bit instruction
and execute.
Shift out the VISI
register.
Reserved.
Description