DSPIC30F4013-20E/PT Microchip Technology, DSPIC30F4013-20E/PT Datasheet - Page 43

• Manufacturer Part Number: DSPIC30F4013-20E/PT
• Description: IC DSPIC MCU/DSP 48K 44TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4013-20E/PT

• Program Memory Type: FLASH
• Program Memory Size: 48KB (16K x 24)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, POR, PWM, WDT
• Number Of I /o: 30
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 30
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
• Minimum Operating Temperature: - 40 C
• Package: 44TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 13-chx12-bit
• Number Of Timers: 5
• Core Frequency: 20MHz
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 30
• Flash Memory Size: 48KB
• Supply Voltage Range: 2.5V To 5.5V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC30F006 - MODULE SKT FOR DSPIC30F 44TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F401320EPT

11.7
The FOSC, FWDT, FBORPOR and FICD registers are
not erasable. It is recommended that all Configuration
registers be set to a default value after erasing program
memory. The FWDT, FBORPOR and FICD registers
can be set to a default all ‘1’s value by programming
0xFFFF to each register. Since these registers contain
unimplemented bits that read as ‘0’ the default values
shown in
The recommended default FOSC value is 0xC100,
which selects the FRC clock oscillator setting.
The FGS, FBS and FSS Configuration registers are
special since they enable code protection for the
device. For security purposes, once any bit in these
registers is programmed to ‘0’ (to enable some code
protection feature), it can only be set back to ‘1’ by
performing a Bulk Erase or Segment Erase as
described
Memory in Normal-Voltage
these bits from a ‘0’ to ‘1’ is not possible, but they may
be programmed from a ‘1’ to a ‘0’ to enable code
protection.
Table 11-7
clearing the Configuration registers. In Step 1, the
Reset vector is exited. In Step 2, the write pointer (W7)
is loaded with 0x0000, which is the original destination
address (in TBLPAG 0xF8 of program memory). In
Step 3, the NVMCON is set to program one Configura-
TABLE 11-7:
© 2010 Microchip Technology Inc.
Step 1: Exit the Reset vector.
0000
0000
0000
Step 2: Initialize the write pointer (W7) for the TBLWT instruction.
0000
Step 3: Set the NVMCON to program 1 Configuration register.
0000
0000
Step 4: Initialize the TBLPAG register.
0000
0000
Step 5: Load the Configuration register data to W6.
0000
0000
Command
(Binary)
Writing Configuration Memory
Table 11-6
shows the ICSP programming details for
in
040100
040100
000000
200007
24008A
883B0A
200F80
880190
2xxxx0
000000
Section 11.5
(Hexadecimal)
SERIAL INSTRUCTION EXECUTION FOR WRITING CONFIGURATION
REGISTERS
will be read instead of 0xFFFF.
Data
Systems”. Programming
“Erasing
GOTO 0x100
GOTO 0x100
NOP
MOV
MOV
MOV
MOV
MOV
MOV
NOP
Program
#0x0000, W7
#0x4008, W10
W10, NVMCON
#0xF8, W0
W0, TBLPAG
#<CONFIG_VALUE>, W0
tion register. In Step 4, the TBLPAG register is
initialized, to 0xF8, for writing to the Configuration
registers. In Step 5, the value to write to the each
Configuration register (0xFFFF) is loaded to W6. In
Step 6, the Configuration register data is written to the
write latch using the TBLWTL instruction. In Steps 7 and
8, the NVMCON is unlocked for programming and the
programming cycle is initiated, as described in
Section 11.4 “Flash Memory Programming in ICSP
Mode”. In Step 9, the internal PC is set to 0x100 as a
safety measure to prevent the PC from incrementing
into unimplemented memory. Lastly, Steps 3-9 are
repeated six times until all seven Configuration
registers are cleared.
TABLE 11-6:
0xF80000
0xF80002
0xF80004
0xF80006
0xF80008
0xF8000A
0xF8000C
Address
Description
FOSC
FWDT
FBORPOR
FBS
FSS
FGS
FICD
DEFAULT CONFIGURATION
REGISTER VALUES
Register
DS70102K-page 43
Default Value
0xC100
0x803F
0x87B3
0x310F
0x330F
0xC003
0x0007