DSPIC30F4013-20E/PT Microchip Technology, DSPIC30F4013-20E/PT Datasheet - Page 5

• Manufacturer Part Number: DSPIC30F4013-20E/PT
• Description: IC DSPIC MCU/DSP 48K 44TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4013-20E/PT

• Program Memory Type: FLASH
• Program Memory Size: 48KB (16K x 24)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, POR, PWM, WDT
• Number Of I /o: 30
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 30
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
• Minimum Operating Temperature: - 40 C
• Package: 44TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 13-chx12-bit
• Number Of Timers: 5
• Core Frequency: 20MHz
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 30
• Flash Memory Size: 48KB
• Supply Voltage Range: 2.5V To 5.5V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC30F006 - MODULE SKT FOR DSPIC30F 44TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F401320EPT

5.0
5.1
Once the programming executive has been verified
in memory (or loaded if not present), the dsPIC30F can
be programmed using the command set shown in
Table
provided in
Commands”.
TABLE 5-1:
A high-level overview of the programming process is
illustrated in
ing Enhanced ICSP mode. The chip is then bulk
erased, which clears all memory to ‘1’ and allows the
device to be programmed. The Chip Erase is verified
before programming begins. Next, the code memory,
data Flash and Configuration bits are programmed. As
these memories are programmed, they are each
verified to ensure that programming was successful. If
no errors are detected, the programming is complete
and Enhanced ICSP mode is exited. If any of the
verifications fail, the procedure should be repeated,
starting from the Chip Erase.
© 2010 Microchip Technology Inc.
SCHECK
READD
READP
PROGD
PROGP
PROGC
ERASEB
ERASED
ERASEP
QBLANK
QVER
Command
5-1. A detailed description for each command is
DEVICE PROGRAMMING
Overview of the Programming
Process
Figure
Section 8.0 “Programming Executive
Sanity check
Read data EEPROM, Configuration
registers and device ID
Read code memory
Program one row of data EEPROM
and verify
Program one row of code memory and
verify
Program Configuration bits and verify
Bulk Erase, or erase by segment
Erase data EEPROM
Erase code memory
Query if the code memory and data
EEPROM are blank
Query the software version
COMMAND SET SUMMARY
5-1. The process begins by enter-
Description
If Advanced Security features are enabled, then
individual Segment Erase operations need to be
performed, based on user selections (i.e., based on the
specific needs of the user application). The specific
operations that are used typically depend on the order
in which various segments need to be programmed for
a given application or system.
Section 5.2 “Entering Enhanced ICSP Mode”
through
describe the programming process in detail.
FIGURE 5-1:
Section 5.8 “Exiting Enhanced ICSP Mode”
Exit Enhanced ICSP
Program and verify
Configuration bits
Enter Enhanced
ICSP™ mode
Perform Chip
Configuration
Program and
Program and
default value
verify code
registers to
verify data
PROGRAMMING FLOW
Program
Finish
Start
Erase
Mode
DS70102K-page 5