ATXMEGA16A4-CU Atmel, ATXMEGA16A4-CU Datasheet - Page 159
ATXMEGA16A4-CU
Manufacturer Part Number
ATXMEGA16A4-CU
Description
MCU AVR 16+4KB FLASH 49VFBGA
Manufacturer
Atmel
Series
AVR® XMEGAr
Specifications of ATXMEGA16A4-CU
Core Processor
AVR
Core Size
8/16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 3.6 V
Data Converters
A/D 12x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
49-VFBGA
Processor Series
ATXMEGA16x
Core
AVR8
Data Bus Width
8 bit, 16 bit
Data Ram Size
2 KB
Interface Type
I2C/SPI/USART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
34
Number Of Timers
5
Operating Supply Voltage
1.6 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
12-ch x 12-bit
On-chip Dac
2-ch x 12-bit
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
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Price
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14.7.4
14.7.5
14.8
8077H–AVR–12/09
Compare Channel
32-bit Input Capture
Capture Overflow
Figure 14-11. Pulse-width capture of external signal.
Two Timer/Counters can be used together to enable true 32-bit Input Capture. In a typical 32-bit
Input Capture setup the overflow event of the least significant timer is connected via the Event
System and used as clock input for the most significant timer.
Since all events are pipelined, the most significant timer will be updated one peripheral clock
period after an overflow occurs for the least significant timer. To compensate for this delay the
capture event for the most significant timer must be equally delayed by setting the Event Delay
bit for this timer.
The Timer/Counter can detect buffer overflow on any of the Input Capture Channels. In the case
where both the Buffer Valid flag and Capture Interrupt Flag are set, and a new capture event is
detected there is nowhere to store the new time-stamp. If a buffer overflow is detected the new
value is rejected, the Error Interrupt Flag is set and the optional interrupt is generated.
Each compare channel continuously compares the counter value (CNT) with the CCx register. If
CNT equals CCx the comparator signals a match. The match will set the CC channel's interrupt
flag at the next timer clock cycle, and the event and optional interrupt is generated.
The compare buffer register provides double buffer capability equivalent to the period buffer.
The double buffering synchronizes the update of the CCx register with the buffer value to either
the TOP or BOTTOM of the counting sequence according to the UPDATE condition signal from
the Timer/Counter control logic. The synchronization prevents the occurrence of odd-length,
non-symmetrical PWM/FRQ pulses, thereby making the output glitch-free.
external signal
events
CNT
MAX
BOT
Pulsewitdh (t
p
)
XMEGA A
"capture"
159
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