ATXMEGA16A4-CU Atmel, ATXMEGA16A4-CU Datasheet - Page 347
ATXMEGA16A4-CU
Manufacturer Part Number
ATXMEGA16A4-CU
Description
MCU AVR 16+4KB FLASH 49VFBGA
Manufacturer
Atmel
Series
AVR® XMEGAr
Specifications of ATXMEGA16A4-CU
Core Processor
AVR
Core Size
8/16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 3.6 V
Data Converters
A/D 12x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
49-VFBGA
Processor Series
ATXMEGA16x
Core
AVR8
Data Bus Width
8 bit, 16 bit
Data Ram Size
2 KB
Interface Type
I2C/SPI/USART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
34
Number Of Timers
5
Operating Supply Voltage
1.6 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
12-ch x 12-bit
On-chip Dac
2-ch x 12-bit
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
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29.3.3.1
29.3.4
8077H–AVR–12/09
Serial transmission and reception
Characters
Table 29-1.
Three different characters, DATA, BREAK and IDLE, are used. The BREAK character is equal
to 12 bit-length of low level. The IDLE character is equal to 12 bit-length of high level. Both the
BREAK and the IDLE character can be extended beyond the bit-length of 12.
Figure 29-5. Characters and timing for the PDI Physical.
The PDI physical layer is either in Transmit (TX) or Receive (RX) mode of operation. By default
it is in RX mode, waiting for a start bit.
The programmer and the PDI operate synchronously on the PDI_CLK provided by the program-
mer. The dependency between the clock edges and data sampling or data change is fixed. As
illustrated in
is always set up (changed) on the falling edge of PDI_CLK, while data is always sampled on the
rising edge of PDI_CLK.
Figure 29-6. Changing and sampling of data.
St
(0-7)
P
Sp1
Sp2
Start bit, always low.
Data bits (0 to 7)
Parity bit, even parity is used
Stop bit 1, always high.
Stop bit 2, always high.
Figure 29-6 on page
PD I_DATA
PDI_CLK
START
0
1
347, output data (either from the programmer or from the PDI)
2
Sam ple
3
1 BREAK character
1 DATA character
1 IDLE character
BREAK
4
IDLE
5
6
Sam ple
7
P
STOP
Sam ple
XMEGA A
347
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