ATMEGA32U4-AU Atmel, ATMEGA32U4-AU Datasheet - Page 129

MCU AVR 32K FLASH 16MHZ 44-TQFP

ATMEGA32U4-AU

Manufacturer Part Number
ATMEGA32U4-AU
Description
MCU AVR 32K FLASH 16MHZ 44-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar

Specifications of ATMEGA32U4-AU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
26
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Processor Series
ATMEGA32x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2.5 KB
Interface Type
SPI/TWI/USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
26
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
12-ch x 10-bit
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
16MHz
Total Internal Ram Size
2.5KB
# I/os (max)
26
Number Of Timers - General Purpose
5
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Package Type
TQFP
Controller Family/series
AVR MEGA
No. Of I/o's
26
Eeprom Memory Size
1KB
Ram Memory Size
2.5KB
Cpu Speed
16MHz
Rohs Compliant
Yes
For Use With
ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ATMEGA32U4-16AU
ATMEGA32U4-16AU

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA32U4-AU
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Atmel
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14.10 16-bit Timer/Counter Register Description
14.10.1
14.10.2
7766F–AVR–11/10
Timer/Counter1 Control Register A – TCCR1A
Timer/Counter3 Control Register A – TCCR3A
Figure 14-13. Timer/Counter Timing Diagram, with Prescaler (f
The COMnA1:0, COMnB1:0, and COMnC1:0 control the output compare pins (OCnA, OCnB,
and OCnC respectively) behavior. If one or both of the COMnA1:0 bits are written to one, the
OCnA output overrides the normal port functionality of the I/O pin it is connected to. If one or
both of the COMnB1:0 bits are written to one, the OCnB output overrides the normal port func-
tionality of the I/O pin it is connected to. If one or both of the COMnC1:0 bits are written to one,
the OCnC output overrides the normal port functionality of the I/O pin it is connected to. How-
ever, note that the Data Direction Register (DDR) bit corresponding to the OCnA, OCnB or
OCnC pin must be set in order to enable the output driver.
and ICF n
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit 7:6 – COMnA1:0: Compare Output Mode for Channel A
Bit 5:4 – COMnB1:0: Compare Output Mode for Channel B
Bit 3:2 – COMnC1:0: Compare Output Mode for Channel C
(PC and PFC PWM)
TOVn
(CTC and FPWM)
(Update at TOP)
TCNTn
TCNTn
as TOP)
OCRnx
(clk
clk
clk
I/O
(FPWM)
I/O
Tn
/8)
(if used
7
COM1A1
R/W
0
7
COM3A1
R/W
0
6
COM1A0
R/W
0
6
COM3A0
R/W
0
TOP - 1
TOP - 1
Old OCRnx Value
5
COM3B1
R/W
0
5
COM1B1
R/W
0
4
COM3B0
R/W
0
4
COM1B0
R/W
0
TOP
TOP
R/W
3
COM3C1
0
3
COM1C1
R/W
0
BOTTOM
TOP - 1
2
COM3C0
R/W
0
2
COM1C0
R/W
0
New OCRnx Value
clk_I/O
ATmega16/32U4
1
WGM31
R/W
0
1
WGM11
R/W
0
/8)
BOTTOM + 1
TOP - 2
WGM30
R/W
0
0
0
WGM10
R/W
0
TCCR3A
TCCR1A
129

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