ATMEGA32U4-AU Atmel, ATMEGA32U4-AU Datasheet - Page 263

MCU AVR 32K FLASH 16MHZ 44-TQFP

ATMEGA32U4-AU

Manufacturer Part Number
ATMEGA32U4-AU
Description
MCU AVR 32K FLASH 16MHZ 44-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar

Specifications of ATMEGA32U4-AU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
26
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Processor Series
ATMEGA32x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2.5 KB
Interface Type
SPI/TWI/USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
26
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
12-ch x 10-bit
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
16MHz
Total Internal Ram Size
2.5KB
# I/os (max)
26
Number Of Timers - General Purpose
5
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Package Type
TQFP
Controller Family/series
AVR MEGA
No. Of I/o's
26
Eeprom Memory Size
1KB
Ram Memory Size
2.5KB
Cpu Speed
16MHz
Rohs Compliant
Yes
For Use With
ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ATMEGA32U4-16AU
ATMEGA32U4-16AU

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21.12 Registers description
21.12.1
7766F–AVR–11/10
USB general registers
Figure 21-13. Plug-in Detection Input Block Diagram
The control logic of the VBUS pad outputs a signal regarding the VBUS voltage level:
• 7-1 – Reserved
These bits are reserved. Do not modify these bits.
• 0 – UVREGE: USB pad regulator Enable
Set to enable the USB pad regulator. Clear to disable the USB pad regulator.
• 7 – USBE: USB macro Enable Bit
Set to enable the USB controller. Clear to disable and reset the USB controller, to disable the
USB transceiver and to disable the USB controller clock inputs.
• 6 – Reserved
The value read from these bits is always 0. Do not set these bits.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
• The “Session_valid” signal is active high when the voltage on the UVBUS pad is higher or
• The VBUS status bit is set when “Session_valid” signal is active (VBUS > 1.4V).
• The VBUSTI flag is set each time the VBUS state changes.
• The USB peripheral cannot attach to the bus while VBUS bit is not set.
equal to 1.4V. If lower than 1.4V, the signal is not active.
VBUS
USBE
R/W
R/W
7
0
7
0
-
R/W
R/W
0
6
-
6
0
-
Pad logic
FRZCLK
R/W
VDD
VSS
R
5
0
5
1
-
OTGPADE
R/W
Session_valid
R/W
4
0
-
4
0
R
3
0
-
R
3
0
-
USBSTA.0
VBUS
R
2
0
-
R
2
0
-
R
R/W
1
0
ATmega16/32U4
-
1
0
-
UVREGE
VBUSTE
R/W
R/W
0
0
0
0
VBUSTI
USBINT.0
UHWCON
USBCON
263

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