PIC16C774/PT Microchip Technology, PIC16C774/PT Datasheet - Page 71
![IC MCU OTP 4KX14 A/D PWM 44TQFP](/photos/6/82/68251/c04-076_pt_sml.jpg)
PIC16C774/PT
Manufacturer Part Number
PIC16C774/PT
Description
IC MCU OTP 4KX14 A/D PWM 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16C773SO.pdf
(201 pages)
3.PIC16C774P.pdf
(13 pages)
4.PIC16C774P.pdf
(16 pages)
Specifications of PIC16C774/PT
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
7KB (4K x 14)
Program Memory Type
OTP
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16C774/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC16C773SO PDF datasheet #2
- PIC16C774P PDF datasheet #3
- PIC16C774P PDF datasheet #4
- Current page: 71 of 201
- Download datasheet (3Mb)
8.2.5
Master mode of operation is supported by interrupt
generation on the detection of the START and STOP
conditions. The STOP (P) and START (S) bits are
cleared from a reset or when the MSSP module is dis-
abled. Control of the I
bit is set, or the bus is idle with both the S and P bits
clear.
FIGURE 8-17: SSP BLOCK DIAGRAM (I
1999 Microchip Technology Inc.
SDA
SCL
MASTER MODE
2
C bus may be taken when the P
SDA in
Bus Collision
SCL in
Read
Advance Information
MSb
Write collision detect
end of XMIT/RCV
Start bit, Stop bit,
Clock Arbitration
State counter for
Start bit detect,
2
Stop bit detect
Acknowledge
C MASTER MODE)
Generate
SSPBUF
SSPSR
LSb
Write
In master mode, the SCL and SDA lines are manipu-
lated by the MSSP hardware.
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP Interrupt if enabled):
• START condition
• STOP condition
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeated Start
clock
data bus
shift
Internal
Set/Reset, S, P, WCOL (SSPSTAT)
Set SSPIF, BCLIF
Reset AKSTAT, PEN (SSPCON2)
PIC16C77X
SSPADD<6:0>
SSPM3:SSPM0,
Baud
rate
generator
DS30275A-page 71
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