DSPIC30F2020-30I/MM Microchip Technology, DSPIC30F2020-30I/MM Datasheet
DSPIC30F2020-30I/MM
Specifications of DSPIC30F2020-30I/MM
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DSPIC30F2020-30I/MM Summary of contents
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... This document includes programming specifications for the following devices: • dsPIC30F1010 • dsPIC30F2020 • dsPIC30F2023 The dsPIC30F SMPS family enters programming modes via the 32-bit serial key sequence clocked into the PGD line, similar to the dsPIC33F family. On the other hand, the programming operations themselves are similar to the other dsPIC30F devices ...
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... TABLE 2-1: CODE MEMORY MAP AND SIZE dsPIC30F SMPS Code Memory Map Device (Size in Instruction Words) dsPIC30F1010 0x000000-0x000FFE (2K) dsPIC30F2020 0x000000-0x001FFE (4K) dsPIC30F2023 0x000000-0x001FFE (4K) TABLE 2-2: PIN DESCRIPTIONS (PINS USED DURING PROGRAMMING) Pin Name Pin Name MCLR MCLR ...
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... FIGURE 2-2: PROGRAM MEMORY MAP Note: The address boundaries for user Flash code memory are device specific. © 2010 Microchip Technology Inc. 000000 User Flash Code Memory (4K x 24-bit) 017FFE 018000 Reserved 7FFFFE 800000 Executive Code Memory (Reserved) 8005BE 8005C0 Unit ID ...
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... Enter ICSP™ Mode Section 5.0 Read the Application ID from Address 0x805BE Is Application ID 0xBB? Prog. Executive is Resident in Memory Finish 4-1. the Programming describes the process Section 11.11 describes the CONFIRMING PRESENCE OF PROGRAMMING EXECUTIVE No Yes Prog. Executive must be Programmed © 2010 Microchip Technology Inc. ...
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... If no errors are detected, the programming is complete and Enhanced ICSP mode is exited. If any of the verifications fail, the procedure should be repeated, starting from the Chip Erase. © 2010 Microchip Technology Inc. FIGURE 5-1: PROGRAMMING FLOW Start Enter Enhanced ICSP™ ...
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... PROGC commands. One PROGC command must be sent for each Configuration register (see Section 5.7 “Configuration Bits Note: The Device ID registers cannot be erased. These registers remain intact after a Chip Erase is performed. must be IH P17 Programming”). © 2010 Microchip Technology Inc. ...
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... A flowchart for programming of code memory is illus- trated in Figure 5-4. In this example, all 4K instruction words of a dsPIC30F2020 device are programmed. First, the number of commands to send (called ‘RemainingCmds’ in the flowchart) is set to 128 and the destination address (called ‘BaseAddress’) is set to ‘0’. ...
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... FRANGE — — — WDTPRE — — — — — — — — Table 5-4 describes the individual Bit 2 Bit 1 Bit 0 BSS<2:0> BWRP — — — GSS<1:0> GWRP — FNOSC<1:0> OSCIOFNC POSCMD<1:0> WDTPOST<3:0> FPWRT<2:0> — ICS<1:0> © 2010 Microchip Technology Inc. ...
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... High security, Small-sized Boot Program Flash [Boot Segment ends at 0x0003FF] 001 = High security, Medium-sized Boot Program Flash [Boot Segment ends at 0x000FFF Note: This is for the dsPIC30F2020 and dsPIC30F2023 only.] 000 = No Boot Segment Boot Segment Program Memory Write Protection 1 = Boot Segment program memory is not write-protected ...
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... Device will reset in User mode 0 = Device will reset in Debug mode ICD Communication Channel Select bits 11 = Communicate on PGC/EMUC and PGD/EMUD 10 = Communicate on PGC1/EMUC1 and PGD1/EMUD1 01 = Communicate on PGC2/EMUC2 and PGD2/EMUD2 00 = Reserved, do not use Unimplemented (read as ‘0’, write as ‘0’) © 2010 Microchip Technology Inc. ...
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... The dsPIC30F SMPS family devices do not contain a Secure Segment. © 2010 Microchip Technology Inc. BWRP and GWRP bits control write protection and BSS<2:0> and GSS<1:0> bits control read protection. ...
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... Programming the UNIT ID is similar to programming the Programming Executive “Programming the Programming Executive to Memory” for details). Start ConfigAddress = 0xF80000 Send PROGC Command Is No PROGC Response PASS? Yes Is No ConfigAddress 0xF8000C? Yes Finish information. (see Section 12.0 Failure Report Error © 2010 Microchip Technology Inc. ...
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... Code protection can only be disabled by performing a Chip Erase with the ERASEB command. © 2010 Microchip Technology Inc. 6.3 Reading Memory The READD command reads the Configuration bits and device ID of the device. This command only returns 16-bit data and operates on 16-bit registers ...
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... Contents of Configuration registers TABLE 6-2: CHECKSUM COMPUTATION Read Code SMPS Device Protection dsPIC30F1010 Disabled Enabled dsPIC30F2020 Disabled Enabled dsPIC30F2023 Disabled Enabled Item Description: SUM(a:b) = Byte sum of locations inclusive (all 3 bytes of code memory) CFGB = Configuration Block (masked) = Byte sum of ((FBS&0x000F)+(FGS&0x0007)+(FOSCSEL&0x0003)+ (FOSC& ...
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... PGD ... MSb © 2010 Microchip Technology Inc. Since a 2-wire SPI interface is used, and data transmissions are bidirectional, a simple protocol is used to control the direction of PGD. When the programmer completes a command transmission, it releases the PGD line and allows the programming executive to drive this line high. The programming executive keeps the PGD line high to indicate that it is processing the command ...
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... PGC PGD MSB LSB P8 PGC = Input PGD = Input DS70284C-page 16 Programming Executive Host Clocks Out Response Processes Command MSB LSB 1 0 P10 P9b P9a PGC = Input (Idle) PGD = Output MSB LSB P11 PGC = Input PGD = Output © 2010 Microchip Technology Inc. ...
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... SPI port. If the value of this field is incorrect, the command will not be properly received by the programming executive. © 2010 Microchip Technology Inc. 8.3 Packed Data Format When 24-bit instruction words are transferred across the 16-bit SPI interface, they are packed to conserve ...
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... Bulk Erase (entire program memory), or erase by segment. 5 Not Implemented. msec/row 5 Erase rows of code memory from specified address. msec/row 300 msec Query if the code memory is blank. 1 msec Query the programming executive software version. Description Table 5-2 for device-specific © 2010 Microchip Technology Inc. ...
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... Expected Response (2 words): 0x1000 0x0002 Note: This instruction is not required for programming, but is development purposes only. © 2010 Microchip Technology Inc. 8.5.2 READD COMMAND programming Opcode “QVER Reserved0 Reserved1 0 ...
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... After all data has been programmed to code memory, the programming executive verifies the programmed data against the data in the command. Expected Response (2 words): 0x1500 0x0002 Note: Refer to Table 5-2 information. © 2010 Microchip Technology Inc Length Addr_MSB ... Description Figure 8-2. for code memory size ...
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... Configuration registers are 16 bits wide, and this command allows one Config- uration register to be programmed. Expected Response (2 words): 0x1600 0x0002 Note: This command can only be used for programming Configuration registers. © 2010 Microchip Technology Inc. 8.5.6 ERASEB COMMAND Opcode Reserved Field ...
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... Expected Response (2 words for non-blank device): 0x1A0F 0x0002 Note: The QBLANK command does not check the system Configuration registers. The READD command must be used to determine the state of the Configuration registers. 0 Length PSize DSize Description © 2010 Microchip Technology Inc. ...
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... PASS Command successfully processed. 0x2 FAIL Command unsuccessfully processed. 0x3 NACK Command not known. © 2010 Microchip Technology Inc. 9.2 Response Format 0 All programming executive responses have a general format consisting of a two-word header and any required data for the command Opcode ...
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... Section 8.3 “Packed Data Format”. When reading an odd number of program memory words (N odd), the response to the READP command is (3 • 1)/ words. When reading an even number of program memory words (N even), the response to the READP command is (3 • N words. © 2010 Microchip Technology Inc. described in ...
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... ID for each device, Table 10-2 shows the device ID registers and Table 10-3 describes the bit field of each register. TABLE 10-1: DEVICE IDs SMPS Device DEVID dsPIC30F1010 0x0404 dsPIC30F2020 0x0400 dsPIC30F2023 0x0403 TABLE 10-2: DEVICE ID REGISTERS Address Name 15 DEVID 0xFF0000 ...
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... CPU idle until the next 4-bit control code is shifted in. Note: Once the contents of VISI are shifted out, ® the dsPIC DSC device maintains PGD as an output until the first rising edge of the next clock is received. © 2010 Microchip Technology Inc. ...
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... P3 P2 LSB X PGD Execute PC – 1, Fetch SIX Control Code FIGURE 11-3: REGOUT SERIAL EXECUTION PGC P4 PGD Execute Previous Instruction, CPU Held In Idle Fetch REGOUT Control Code PGD = Input © 2010 Microchip Technology Inc P1A P1B LSB 24-bit Instruction Fetch PGD = Input ...
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... On successful entry, the program memory can be accessed and programmed in serial fashion. While in ICSP mode, all unused I/Os are placed in the high-impedance state Program/Verify Entry Code = 0x4D434851 ... b31 b30 b29 b28 b27 b3 P2B P2A remembered as 0x4D434851 in must be IH P17 © 2010 Microchip Technology Inc. ...
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... Write Operation Value 0x4008 Writes 1 word to configuration memory. 0x4001 Writes 1 row (32 instruction words) into 1 panel of program memory. © 2010 Microchip Technology Inc. 11.4.2 UNLOCKING NVMCON FOR PROGRAMMING Writes to the WR bit (NVMCON<15>) are locked to described in prevent accidental programming from taking place. through ...
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... Requirements”) 0000 A9E761 BCLR NVMCON, #WR 0000 000000 NOP 0000 000000 NOP 0000 000000 NOP 0000 000000 NOP DS70284C-page 30 Description #0x407F, W10 W10, NVMCON #0x55, W8 W8, NVMKEY #0xAA, W9 W9, NVMKEY (see Section 13.0 “AC/DC Characteristics and Timing © 2010 Microchip Technology Inc. ...
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... NOP 0000 000000 NOP 0000 000000 NOP © 2010 Microchip Technology Inc. Table 11- Segment Erase operation is required, Step 3 must be modified with the appropriate NVMCON value as per Table However, since this method is more time consuming and does not clear the code-protect bits not recommended in most cases ...
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... Step 15: Repeat Steps 10-14 until all 24 rows of executive memory are erased. DS70284C-page 32 Description W6, W7, W6 SR, #C NVMADRU W6, NVMADR W6 W6, NVMADR #0x80, W7 W7, NVMADRU #0x40, W7 #0x4071, W10 W10, NVMCON #0x55, W8 W8, NVMKEY #0xAA, W9 W9, NVMKEY (see Section 13.0 “AC/DC Characteristics and Timing W6, W7, W6 W6, NVMADR © 2010 Microchip Technology Inc. ...
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... MOV 0000 883B39 MOV © 2010 Microchip Technology Inc. is initialized to 0xF8 for writing to the Configuration registers. In Step 5, the value to write to each Configuration register (0xFFFF) is loaded to W6. In Step 6, the Configuration register data is written to the write latch using the TBLWTL instruction. In Steps 7 and ...
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... NOP 0000 000000 NOP Step 9: Reset device internal PC. 0000 040100 GOTO 0x100 0000 000000 NOP Step 10: Repeat steps 3-9 until all seven Configuration registers are programmed. DS70284C-page 34 Description (see Section 13.0 “AC/DC Characteristics and Timing © 2010 Microchip Technology Inc. ...
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... MOV 0000 2xxxx5 MOV © 2010 Microchip Technology Inc. Since code memory is programmed 32 instruction words at a time, Steps 4 and 5 are repeated eight times to load all the write latches (Step 6). After the write latches are loaded, programming is initiated by writing to the NVMKEY and NVMCON registers in Steps 7 and 8 ...
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... NOP Step 10: Repeat steps 2-9 until all code memory is programmed. DS70284C-page 36 Description W6 [W6++], [W7] [W6++], [W7++] [W6++], [++W7] [W6++], [W7++] [W6++], [W7] [W6++], [W7++] [W6++], [++W7] [W6++], [W7++] #0x55, W8 W8, NVMKEY #0xAA, W9 W9, NVMKEY NVMCON, #WR (see Section 13.0 “AC/DC Characteristics and Timing NVMCON, #WR © 2010 Microchip Technology Inc. ...
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... NOP 0000 000000 NOP © 2010 Microchip Technology Inc. To minimize the reading time, the packed instruction word format that was utilized for writing is also used for reading (see Figure W7 is initialized, and four instruction words are read from code memory and stored to working registers W0:W5 ...
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... Clock out contents of VISI register 0000 000000 NOP Step 5: Reset the device internal PC. 0000 040100 GOTO 0x100 0000 000000 NOP Step 6: Repeat steps 4-5 until all desired code memory is read. DS70284C-page 38 Description W0, VISI W1, VISI W2, VISI W3, VISI W4, VISI W5, VISI © 2010 Microchip Technology Inc. ...
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... NOP Step 6: Repeat steps 3-5 until all desired code memory is read. © 2010 Microchip Technology Inc. Table 11-10 shows the ICSP programming details for reading all of the configuration memory. Note that the TBLPAG register is hard-coded to 0xF8 (the upper byte address of configuration memory), and the read pointer W6 is initialized to 0x0000 ...
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... PGC and PGD before removing V FIGURE 11-6: MCLR V DD PGD PGC Programming Description #0x80, W0 W0, TBLPAG #0x5BE, W0 VISI, W1 from IH Figure 11-6. The only require EXITING ICSP™ MODE P9b P15 PGD = Input © 2010 Microchip Technology Inc. ...
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... NOP 0000 000000 NOP © 2010 Microchip Technology Inc. Storing the programming executive to executive memory is similar to normal programming of code memory. Namely, the executive memory must first be erased, and then the programming executive must be programmed 32 words at a time. This control flow is ...
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... Step 13: Repeat Steps 7-12 until all 23 rows of executive memory are programmed. DS70284C-page 42 Description #<LSW0>, W0 #<MSB1:MSB0>, W1 #<LSW1>, W2 #<LSW2>, W3 #<MSB3:MSB2>, W4 #<LSW3> [W6++], [W7] [W6++], [W7++] [W6++], [++W7] [W6++], [W7++] [W6++], [W7] [W6++], [W7++] [W6++], [++W7] [W6++], [W7++] #0x55, W8 W8, NVMKEY #0xAA, W9 W9, NVMKEY (see Section 13.0 “AC/DC Characteristics and Timing © 2010 Microchip Technology Inc. ...
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... TBLRDL 0000 000000 NOP 0000 000000 NOP © 2010 Microchip Technology Inc. Reading the contents of executive memory can be performed using the similar technique described in has been Section 11.9 “Reading Code for reading executive memory is shown in Note that, in Step 2, the TBLPAG register is set to 0x80 such that executive memory may be read ...
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... Clock out contents of VISI register Step 5: Reset the device internal PC. 0000 040100 GOTO 0x100 0000 000000 NOP Step 6: Repeat Steps 3-5 until all 736 instruction words of executive memory are read. DS70284C-page 44 Description W0, VISI W1, VISI W2, VISI W3, VISI W4, VISI W5, VISI © 2010 Microchip Technology Inc. ...
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... Processing Time Delay between PGD ↓ by Programming P9b T 5 DLY Executive to PGD Released by Programming Executive P10 T 6 PGC Low Time After Programming DLY © 2010 Microchip Technology Inc. Standard Operating Conditions (unless otherwise stated) Operating Temperature: 25° recommended Min Max Units Conditions 0 — ...
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... Max Units Conditions — ms — 1.0 ms — — ns — — s — 100 ns — — ns — — ns — ICSP mode 2.6 ms Enhanced ICSP mode 4 ms ICSP mode 2.6 ms Enhanced ICSP mode © 2010 Microchip Technology Inc. ...
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... two-digit hexadecimal checksum that is the two’s complement of the sum of all the preceding bytes in the line record. © 2010 Microchip Technology Inc. Because the Intel hex file format is byte-oriented, and the 16-bit program counter is not, program memory sections require special treatment. Each 24-bit program word is extended to 32 bits by inserting a so-called “ ...
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... Device IDs Table 10-2: 10-3: Device ID Bits Description 11-1: Program Entry After Reset Section 11.3 “Entering ICSP Section 11.6 “Row Erasing Table 11-5: Serial Table 11-7: Serial Instruction Table 11-8: Serial Instruction Table 12-1: Table 13-1: © 2010 Microchip Technology Inc. ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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