ATMEGA6490A-AU Atmel, ATMEGA6490A-AU Datasheet - Page 106
ATMEGA6490A-AU
Manufacturer Part Number
ATMEGA6490A-AU
Description
IC MCU AVR 64K FLASH 100TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA6490A-AU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFQFP
Processor Series
ATmega
Core
AVR
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
SPI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
69
Number Of Timers
3
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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8284A–AVR–10/10
Figure 14-7. Phase Correct PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The
Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM
value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the
OC0A pin. Setting the COM0A1:0 bits to two will produce a non-inverted PWM. An inverted
PWM output can be generated by setting the COM0A1:0 to three (See
The actual OC0A value will only be visible on the port pin if the data direction for the port pin is
set as output. The PWM waveform is generated by clearing (or setting) the OC0A Register at the
compare match between OCR0A and TCNT0 when the counter increments, and setting (or
clearing) the OC0A Register at compare match between OCR0A and TCNT0 when the counter
decrements. The PWM frequency for the output when using phase correct PWM can be calcu-
lated by the following equation:
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR0A Register represent special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCR0A is set equal to BOTTOM, the
output will be continuously low and if set equal to MAX the output will be continuously high for
non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.
At the very start of period 2 in
there is no Compare Match. The point of this transition is to guarantee symmetry around BOT-
TOM. There are two cases that give a transition without Compare Match.
• OCR0A changes its value from MAX, like in
OCn pin value is the same as the result of a down-counting Compare Match. To ensure
ATmega169A/169PA/329A/329PA/649A/649P/3290A/3290PA/6490A/6490P
TCNTn
OCn
OCn
Period
1
Figure 14-7
f
OCnxPCPWM
OCn has a transition from high to low even though
2
Figure
=
----------------- -
N 510
f
14-7. When the OCR0A value is MAX the
clk_I/O
⋅
3
Table 17-5 on page
OCnx Interrupt Flag Set
OCRnx Update
TOVn Interrupt Flag Set
(COMnx1:0 = 2)
(COMnx1:0 = 3)
162).
106
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