AT32UC3B0256-Z2UR Atmel, AT32UC3B0256-Z2UR Datasheet - Page 396
![MCU AVR32 256K FLASH 64-QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
AT32UC3B0256-Z2UR
Manufacturer Part Number
AT32UC3B0256-Z2UR
Description
MCU AVR32 256K FLASH 64-QFN
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet
1.AT32UC3B164-AUR.pdf
(680 pages)
Specifications of AT32UC3B0256-Z2UR
Package / Case
64-QFN
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Speed
60MHz
Number Of I /o
44
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
32K x 8
Program Memory Size
256KB (256K x 8)
Data Converters
A/D 8x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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22.7.3.8
22.7.3.9
22.7.3.10
32059J–12/2010
Remote wake-up
Management of control pipes
Management of IN pipes
The controller host mode enters the Suspend state when the UHCON.SOFE bit is written to
zero. No more “Start of Frame” is sent on the USB bus and the USB device enters the Suspend
state 3ms later.
The device awakes the host by sending an Upstream Resume (Remote Wake-Up feature).
When the host controller detects a non-idle state on the USB bus, it set the Host Wake-Up inter-
rupt (HWUPI) bit in UHINT. If the non-idle bus state corresponds to an Upstream Resume (K
state), the Upstream Resume Received Interrupt (RXRSMI) bit in UHINT is set. The user has to
generate a Downstream Resume within 1ms and for at least 20ms by writing a one to the Send
USB Resume (RESUME) bit in UHCON. It is mandatory to write a one to UHCON.SOFE before
writing a one to UHCON.RESUME to enter the Ready state, else UHCON.RESUME will have no
effect.
A control transaction is composed of three stages:
• SETUP
• Data (IN or OUT)
• Status (OUT or IN)
The user has to change the pipe token according to each stage.
For the control pipe, and only for it, each token is assigned a specific initial data toggle
sequence:
• SETUP: Data0
• IN: Data1
• OUT: Data1
IN packets are sent by the USB device controller upon IN requests from the host. All the data
can be read which acknowledges or not the bank when it is empty.
The pipe must be configured first.
When the host requires data from the device, the user has to select beforehand the IN request
mode with the IN Request Mode bit in the Pipe n IN Request register (UPINRQn.INMODE):
• When INMODE is written to zero, the USBB will perform (INRQ + 1) IN requests before
• When INMODE is written to one, the USBB will perform IN requests endlessly when the pipe is
The generation of IN requests starts when the pipe is unfrozen (the Pipe Freeze (PFREEZE)
field in UPCONn is zero).
The Received IN Data Interrupt (RXINI) bit in UPSTAn is set at the same time as the FIFO Con-
trol (FIFOCON) bit in UPCONn when the current bank is full. This triggers a PnINT interrupt if the
Received IN Data Interrupt Enable (RXINE) bit in UPCONn is one.
RXINI shall be cleared by software (by writing a one to the Received IN Data Interrupt Clear bit
in the Pipe n Control Clear register(UPCONnCLR.RXINIC)) to acknowledge the interrupt, what
has no effect on the pipe FIFO.
freezing the pipe.
not frozen by the user.
AT32UC3B
396
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