AT32UC3B0256-Z2UR Atmel, AT32UC3B0256-Z2UR Datasheet - Page 614
![MCU AVR32 256K FLASH 64-QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
AT32UC3B0256-Z2UR
Manufacturer Part Number
AT32UC3B0256-Z2UR
Description
MCU AVR32 256K FLASH 64-QFN
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet
1.AT32UC3B164-AUR.pdf
(680 pages)
Specifications of AT32UC3B0256-Z2UR
Package / Case
64-QFN
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Speed
60MHz
Number Of I /o
44
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
32K x 8
Program Memory Size
256KB (256K x 8)
Data Converters
A/D 8x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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27.5.3.8
32059J–12/2010
AVR_RESET
6. Scan in an 16-bit counter value.
7. Go to Update-DR and re-enter Select-DR Scan.
8. In Shift-DR: Scan out the busy bit, and until the busy bit clears goto 7.
9. Calculate an approximation to the internal clock speed using the elapsed time and the
10. Return to Run-Test/Idle.
The full 16-bit counter value must be provided when starting the synch operation, or the result
will be undefined. When reading status, shifting may be terminated once the required number of
bits have been acquired.
Table 27-23. SYNC_ACCESS Details
This instruction allows a debugger or tester to directly control separate reset domains inside the
chip. The shift register contains one bit for each controllable reset domain. Setting a bit to one
resets that domain and holds it in reset. Setting a bit to zero releases the reset for that domain.
The AVR_RESET instruction can be used in the following way:
1. Select the IR Scan path.
2. In Capture-IR: The IR output value is latched into the shift register.
3. In Shift-IR: The instruction register is shifted by the TCK input.
4. Return to Run-Test/Idle.
5. Select the DR Scan path.
6. In Shift-DR: Scan in the value corresponding to the reset domains the JTAG master
7. Return to Run-Test/Idle.
8. Stay in run test idle for at least 10 TCK clock cycles to let the reset propagate to the
See the device specific documentation for the number of reset domains, and what these
domains are.
For any operation, all bits must be provided or the result will be undefined.
Table 27-24. AVR_RESET Details
Instructions
IR input value
IR output value
DR Size
DR input value
DR output value
Instructions
IR input value
IR output value
counter value.
wants to reset into the data register.
system.
Details
10111 (0x17)
peb01
16 bits
dddddddd dddddddd
xxxxxxxx xxxxxxeb
Details
01100 (0x0C)
p0001
AT32UC3B
614
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