AT91SAM9R64-CU-999 Atmel, AT91SAM9R64-CU-999 Datasheet - Page 156
AT91SAM9R64-CU-999
Manufacturer Part Number
AT91SAM9R64-CU-999
Description
IC MCU ARM9 64K SRAM 144LFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM9R64-CU.pdf
(903 pages)
Specifications of AT91SAM9R64-CU-999
Core Processor
ARM9
Core Size
16/32-Bit
Speed
240MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
AC'97, POR, PWM, WDT
Number Of I /o
49
Program Memory Size
32KB (32K x 8)
Program Memory Type
ROM
Ram Size
72K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Data Converters
A/D 3x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
SPI, TWI, UART
Maximum Clock Frequency
240 MHz
Number Of Programmable I/os
118
Operating Supply Voltage
1.65 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM9RL-EK
Minimum Operating Temperature
- 40 C
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- Current page: 156 of 903
- Download datasheet (13Mb)
21.7.3
21.7.3.1
21.7.3.2
156
AT91SAM9R64/RL64 Preliminary
8-bit NAND Flash
Hardware Configuration
Software Configuration
(ANY PIO)
NANDOE
NANDWE
(ANY PIO)
D[0..7]
CLE
ALE
The following configuration has to be performed:
• Assign the EBI CS3 to the NAND Flash by setting the bit EBI_CS3A in the EBI Chip Select
• Reserve A21 / A22 for ALE / CLE functions. Address and Command Latches are controlled
• NANDOE and NANDWE signals are multiplexed with PIO lines and thus the dedicated PIOs
• A21/NANDALE and A22/NANDCLE signals are multiplexed with PIO lines and thus the
• Configure a PIO line as an input to manage the Ready/Busy signal.
• Configure Static Memory Controller CS3 Setup, Pulse, Cycle and Mode accordingly to NAND
Assignment Register located in the bus matrix memory space
respectively by setting to 1 the address bit A21 and A22 during accesses.
must be programmed in peripheral mode in the PIO controller.
dedicated PIOs must be programmed in peripheral mode in the PIO controller.
Flash timings, the data bus width and the system bus frequency.
3V3
R1
R1
R2
R2
10K
10K
10K
10K
16
17
18
19
10
11
14
15
20
21
22
23
24
25
26
8
9
7
1
2
3
4
5
6
U1
U1
CLE
ALE
RE
WE
CE
R/B
WP
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
TSOP48 PACKAGE
2 Gb
K9F2G08U0M
K9F2G08U0M
PRE
VCC
VCC
VSS
VSS
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
29
30
31
32
41
42
43
44
48
47
46
45
40
39
38
35
34
33
28
27
37
12
36
13
D0
D1
D2
D3
D4
D5
D6
D7
C1
C1
100NF
100NF
3V3
6289C–ATARM–28-May-09
C2
C2
100NF
100NF
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