AT91SAM9R64-CU-999 Atmel, AT91SAM9R64-CU-999 Datasheet - Page 798
AT91SAM9R64-CU-999
Manufacturer Part Number
AT91SAM9R64-CU-999
Description
IC MCU ARM9 64K SRAM 144LFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM9R64-CU.pdf
(903 pages)
Specifications of AT91SAM9R64-CU-999
Core Processor
ARM9
Core Size
16/32-Bit
Speed
240MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
AC'97, POR, PWM, WDT
Number Of I /o
49
Program Memory Size
32KB (32K x 8)
Program Memory Type
ROM
Ram Size
72K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Data Converters
A/D 3x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
SPI, TWI, UART
Maximum Clock Frequency
240 MHz
Number Of Programmable I/os
118
Operating Supply Voltage
1.65 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM9RL-EK
Minimum Operating Temperature
- 40 C
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
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Part Number
Manufacturer
Quantity
Price
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AT91SAM9R64/RL64 Preliminary
UDPHS DMA Channel Transfer Descriptor
The DMA channel transfer descriptor is loaded from the memory.
Be careful with the alignment of this buffer.
The structure of the DMA channel transfer descriptor is defined by three parameters as
described below:
Offset 0:
Offset 4:
Offset 8:
To use the DMA channel transfer descriptor, fill the structures with the correct value (as
described in the following pages).
Then write directly in UDPHS_DMANXTDSCx the address of the descriptor to be used first.
Then write 1 in the LDNXT_DSC bit of UDPHS_DMACONTROLx (load next channel transfer
descriptor). The descriptor is automatically loaded upon Endpointx request for packet transfer.
The address must be aligned: 0xXXXX0
Next Descriptor Address Register: UDPHS_DMANXTDSCx
The address must be aligned: 0xXXXX4
DMA Channelx Address Register: UDPHS_DMAADDRESSx
The address must be aligned: 0xXXXX8
DMA Channelx Control Register: UDPHS_DMACONTROLx
6289C–ATARM–28-May-09
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