ATMEGA128-16AN Atmel, ATMEGA128-16AN Datasheet - Page 191
ATMEGA128-16AN
Manufacturer Part Number
ATMEGA128-16AN
Description
MCU AVR 128KB FLASH 16MHZ 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA128-16AN
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
JTAG
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
53
Number Of Timers
4
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
On-chip Dac
10 bit, 8 Channel
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Price
Company:
Part Number:
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Manufacturer:
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USART Baud Rate
Registers – UBRRnL
and UBRRnH
2467V–AVR–02/11
• Bit 3 – USBSn: Stop Bit Select
This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores
this setting.
Table 79. USBSn Bit Settings
• Bit 2:1 – UCSZn1:0: Character Size
The UCSZn1:0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits
(character size) in a frame the Receiver and Transmitter use.
Table 80. UCSZn Bits Settings
• Bit 0 – UCPOLn: Clock Polarity
This bit is used for synchronous mode only. Write this bit to zero when Asynchronous mode is
used. The UCPOLn bit sets the relationship between data output change and data input sample,
and the synchronous clock (XCKn).
Table 81. UCPOLn Bit Settings
UBRRnH is not available in mega103 compatibility mode
Bit
Read/Write
Initial Value
UCPOLn
0
1
UCSZn2
0
0
0
0
1
1
1
1
Transmitted Data Changed (Output of
TxDn Pin)
Rising XCKn Edge
Falling XCKn Edge
USBSn
R/W
15
R
–
7
0
0
0
1
R/W
UCSZn1
14
R
–
6
0
0
0
0
1
1
0
0
1
1
R/W
13
R
–
5
0
0
R/W
12
R
–
4
0
0
UBRRn[7:0]
UCSZn0
0
1
0
1
0
1
0
1
R/W
R/W
11
3
0
0
Received Data Sampled (Input on
RxDn Pin)
Falling XCKn Edge
Rising XCKn Edge
Stop Bit(s)
R/W
R/W
Character Size
5-bit
6-bit
7-bit
8-bit
Reserved
Reserved
Reserved
9-bit
10
UBRRn[11:8]
2
0
0
2-bits
1-bit
R/W
R/W
9
1
0
0
R/W
R/W
ATmega128
8
0
0
0
UBRRnH
UBRRnL
191
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