ATMEGA128-16AN Atmel, ATMEGA128-16AN Datasheet - Page 278
ATMEGA128-16AN
Manufacturer Part Number
ATMEGA128-16AN
Description
MCU AVR 128KB FLASH 16MHZ 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA128-16AN
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
JTAG
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
53
Number Of Timers
4
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
On-chip Dac
10 bit, 8 Channel
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Addressing the
Flash During Self-
Programming
278
ATmega128
or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire
page write operation if the NRWW section is addressed.
• Bit 0 – SPMEN: Store Program Memory Enable
This bit enables the SPM instruction for the next four clock cycles. If written to one together with
either RWWSRE, BLBSET, PGWRT’ or PGERS, the following SPM instruction will have a spe-
cial meaning, see description above. If only SPMEN is written, the following SPM instruction will
store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer. The LSB of
the Z-pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction,
or if no SPM instruction is executed within four clock cycles. During page erase and page write,
the SPMEN bit remains high until the operation is completed.
Writing any other combination than “10001”, “01001”, “00101”, “00011” or “00001” in the lower
five bits will have no effect.
The Z-pointer together with RAMPZ are used to address the SPM commands. For details on
how to use the RAMPZ, see “RAM Page Z Select Register – RAMPZ” on page 13.
Since the Flash is organized in pages (see
treated as having two different sections. One section, consisting of the least significant bits, is
addressing the words within a page, while the most significant bits are addressing the pages.
This is shown in
independently. Therefore it is of major importance that the Boot Loader software addresses the
same page in both the page erase and page write operation. Once a programming operation is
initiated, the address is latched and the Z-pointer/RAMPZ can be used for other operations.
The only SPM operation that does not use the Z-pointer/RAMPZ is setting the Boot Loader Lock
bits. The content of the Z-pointer/RAMPZ is ignored and will have no effect on the operation.
The (E)LPM instruction does also use the Z-pointer/RAMPZ to store the address. Since this
instruction addresses the Flash byte by byte, also the LSB (bit Z0) of the Z-pointer is used.
Bit
ZH (R31)
ZL (R30)
Z15
15
Z7
7
Figure
Z14
134. Note that the page erase and page write operations are addressed
14
Z6
6
Z13
13
Z5
5
Z12
12
Z4
4
Table 123 on page
Z11
11
Z3
3
Z10
10
Z2
2
291), the program counter can be
Z9
Z1
9
1
Z8
Z0
8
0
2467V–AVR–02/11
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