AT89C5132-RORUL Atmel, AT89C5132-RORUL Datasheet - Page 6
![MCU 8051 FLASH USB 80TQFP](/photos/12/13/121358/313-80-tqfp_sml.jpg)
AT89C5132-RORUL
Manufacturer Part Number
AT89C5132-RORUL
Description
MCU 8051 FLASH USB 80TQFP
Manufacturer
Atmel
Series
AT89C513xr
Specifications of AT89C5132-RORUL
Core Processor
C52X2
Core Size
8-Bit
Speed
20MHz
Connectivity
IDE/ATAPI, I²C, MMC, PCM, SPI, UART/USART, USB
Peripherals
I²S, POR, WDT
Number Of I /o
44
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.3 V
Data Converters
A/D 2x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TQFP, 80-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
8
AT89C5132
Table 3. Timer 0 and Timer 1 Signal Description
Table 4. Audio Interface Signal Description
Table 5. USB Controller Signal Description
Table 6.
Signal
Signal
Signal
Name
Name
Name
DOUT
DCLK
DSEL
SCLK
INT0
INT1
D+
T0
T1
D-
Type
Type
Type
I/O
I/O
O
O
O
O
I
I
I
I
Description
Timer 0 Gate Input
INT0 serves as external run control for timer 0, when selected by
GATE0 bit in TCON register.
External Interrupt 0
INT0 input sets IE0 in the TCON register. If bit IT0 in this register is set,
bit IE0 is set by a falling edge on INT0#. If bit IT0 is cleared, bit IE0 is
set by a low level on INT0#.
Timer 1 Gate Input
INT1 serves as external run control for timer 1, when selected by
GATE1 bit in TCON register.
External Interrupt 1
INT1 input sets IE1 in the TCON register. If bit IT1 in this register is set,
bit IE1 is set by a falling edge on INT1#. If bit IT1 is cleared, bit IE1 is
set by a low level on INT1#.
Timer 0 External Clock Input
When timer 0 operates as a counter, a falling edge on the T0 pin
increments the count.
Timer 1 External Clock Input
When timer 1 operates as a counter, a falling edge on the T1 pin
increments the count.
Description
DAC Data Bit Clock
DAC Audio Data
DAC Channel Select Signal
DSEL is the sample rate clock output.
DAC System Clock
SCLK is the oversampling clock synchronized to the digital audio data
(DOUT) and the channel selection signal (DSEL).
Description
USB Positive Data Upstream Port
This pin requires an external 1.5 KΩ pull-up to V
operation.
USB Negative Data Upstream Port
DD
for full speed
4173CS–USB–07/04
Alternate
Alternate
Alternate
Function
Function
Function
P3.2
P3.3
P3.4
P3.5
-
-
-
-
-
-