AT89C51ED2-RLTUM Atmel, AT89C51ED2-RLTUM Datasheet - Page 51

IC 8051 MCU FLASH 64K 44VQFP

AT89C51ED2-RLTUM

Manufacturer Part Number
AT89C51ED2-RLTUM
Description
IC 8051 MCU FLASH 64K 44VQFP
Manufacturer
Atmel
Series
89Cr
Datasheet

Specifications of AT89C51ED2-RLTUM

Core Processor
8051
Core Size
8-Bit
Speed
60MHz
Connectivity
SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
34
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Cpu Family
89C
Device Core
8051
Device Core Size
8b
Frequency (max)
40MHz
Interface Type
SPI/UART
Total Internal Ram Size
2KB
# I/os (max)
34
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Package Type
VQFP
Processor Series
AT89x
Core
8051
Data Bus Width
8 bit
Data Ram Size
2 KB
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
34
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Minimum Operating Temperature
- 40 C
Package
44VQFP
Family Name
AT89
Maximum Speed
40 MHz
For Use With
AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Compliant

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Manufacturer
Quantity
Price
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AT89C51ED2-RLTUM
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20 000
14.3
14.4
4235K–8051–05/08
Registers
Baud Rate Selection for UART for Mode 1 and 3
Table 14-1.
SADEN - Slave Address Mask Register (B9h)
Reset Value = 0000 0000b
Not bit addressable
Table 14-2.
SADDR - Slave Address Register (A9h)
Reset Value = 0000 0000b
Not bit addressable
The Baud Rate Generator for transmit and receive clocks can be selected separately via the
T2CON and BDRCON registers.
Figure 14-4. Baud Rate Selection
7
7
TIMER1
TIMER2
TIMER1
TIMER2
INT_BRG
INT_BRG
SADEN Register
SADDR Register
6
6
RCLK
TCLK
0
1
0
1
5
5
TIMER_BRG_RX
TIMER_BRG_TX
4
4
3
3
RBCK
TBCK
0
1
0
1
AT89C51RD2/ED2
2
2
/ 16
/ 16
Rx Clock
Tx Clock
1
1
0
0
51

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