AT91CAP7E-NA-ZJ Atmel, AT91CAP7E-NA-ZJ Datasheet - Page 153
AT91CAP7E-NA-ZJ
Manufacturer Part Number
AT91CAP7E-NA-ZJ
Description
MCU CAP7 FPGA 225LFBGA
Manufacturer
Atmel
Series
CAP™r
Specifications of AT91CAP7E-NA-ZJ
Core Processor
ARM7
Core Size
16/32-Bit
Speed
80MHz
Connectivity
EBI/EMI, FPGA, IrDA, SPI, UART/USART, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
ROM
Ram Size
160K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
225-LFBGA
Processor Series
AT91Mx
Core
ARM7TDMI
Data Bus Width
32 bit
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Figure 21-23. TDF Optimization Disabled (TDF Mode = 0). TDF wait states between 2 read accesses on different chip
Figure 21-24. TDF Mode = 0: TDF wait states between a read and a write access on different chip selects
8549A–CAP–10/08
read1 controlling signal
read2 controlling signal
write2 controlling signal
read1 controlling signal
NBS0, NBS1,
NBS2, NBS3,
A0, A1
NBS0, NBS1,
NBS2, NBS3,
A0, A1
A [25:2]
A[ 25:2]
D[31:0]
D[31:0]
(NRD)
(NRD)
(NWE)
(NRD)
selects
MCK
MCK
TDF_CYCLES = 6
TDF_CYCLES = 4
read1 cycle
read1 cycle
read1 hold = 1
read1 hold = 1
Chip Select Wait State
TDF_CYCLES = 4
Read to Write
Wait State
TDF_CYCLES = 6
Chip Select
Wait State
2 TDF WAIT STATES
5 TDF WAIT STATES
write2 setup = 1
(optimization disabled)
TDF_MODE = 0
write2 cycle
AT91CAP7E
(optimization disabled)
TDF_MODE = 0
read2 setup = 1
read 2 cycle
153
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