AT91CAP7E-NA-ZJ Atmel, AT91CAP7E-NA-ZJ Datasheet - Page 210
AT91CAP7E-NA-ZJ
Manufacturer Part Number
AT91CAP7E-NA-ZJ
Description
MCU CAP7 FPGA 225LFBGA
Manufacturer
Atmel
Series
CAP™r
Specifications of AT91CAP7E-NA-ZJ
Core Processor
ARM7
Core Size
16/32-Bit
Speed
80MHz
Connectivity
EBI/EMI, FPGA, IrDA, SPI, UART/USART, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
ROM
Ram Size
160K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
225-LFBGA
Processor Series
AT91Mx
Core
ARM7TDMI
Data Bus Width
32 bit
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Figure 24-4. Divider and PLL Block Diagram
24.1.5.1
Figure 24-5. PLL Capacitors and Resistors
210
AT91CAP7E
PLL Filter
MAINCK
The PLLA requires connection to an external second-order filter through the PLLRCA pin.
24-5
PLLB has its own internal filter which is tuned for optimum operation with a 12 MHz input clock
frequency and an output frequency of 96 MHz for generating the USB clock. Use of any other
frequency for the input clock or output setting for PLLB will likely result in increased jitter and
reduced quality of the PLLB output clock.
Values of R, C1 and C2 to be connected to the PLLRC pin must be calculated as a function of
the PLL input frequency, the PLL output frequency and the phase margin. A trade-off has to be
found between output signal overshoot and startup time.
SLCK
shows a schematic of this filter.
C2
Divider B
Divider A
C1
R
DIVB
DIVA
PLLRC
GND
PLLRCA
MULB
MULA
PLLBCOUNT
PLLACOUNT
Counter
Counter
PLL B
PLL A
PLL B
PLL A
PLL
OUTB
OUTA
LOCKB
LOCKA
PLLBCK
PLLACK
8549A–CAP–10/08
Figure
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